Abstract: A 3-value input buffer circuit is configured by a first N-channel MOS transistor whose source is connected to an input terminal, a first P-channel MOS transistor which is connected to the first N-channel MOS transistor, a first inverter whose input is connected to a drain of the first P-channel MOS transistor, a second P-channel MOS transistor whose source is connected to the input terminal, a second N-channel MOS transistor which is connected to the second P-channel MOS transistor, a second inverter which is connected to a drain of the second N-channel MOS transistor, and a voltage applying circuit which is constituted by P-channel MOS transistors and which applies a constant voltage to a gate of each of the first N-channel MOS transistor and the second P-channel MOS transistor. The first N-channel MOS transistor and the second P-channel MOS transistor are cut off when the input terminal is in an open state. Thus, the power consumption can be significantly suppressed.

Abstract: A power supply voltage monitoring circuit for use in a semiconductor circuit which is used with a plurality of power supply systems and is operable by switching the high and low power supply voltages, includes at least two power supply lines, a reference voltage source, a first comparator, a second comparator and a switching transistor disposed between the first comparator and second comparator. The first comparator operates under a threshold value of a supply voltage which is an intermediate voltage between the high and low power supply voltages. The second comparator receives a voltage to be compared with a reference voltage supplied from the reference voltage source and the switching transistor changes, in response to an output from the first comparator, a voltage to be compared by the second comparator. An alarm signal indicating as to whether the supply voltage is normal or abnormal is obtained at an output of the second comparator.