Abstract: A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to which an input signal is applied, an output terminal from which and output signal is derived, and a set and/or reset terminal to which a set and/or reset signal is applied. The latch circuit has an active mode where a latch function is operable and a sleep mode where the latch function is inoperable, one of which is alternatively selected. The output signal is set or reset to have a specific logic state by the set or reset signal having a specific logic level applied to the set or reset terminal in the active mode.

Abstract: A semiconductor integrated logic circuit device with a sequential circuit includes a transferring section, an inverting section, a bistable circuit section, and a blocking section. The transferring section is provided between first and second nodes, and transfers a data signal from the first node to the second node in response to a clock signal. The inverting section is provided between the second node and a third node, and inverts the data signal on the second node to output on the third node as an inverted data signal. The bistable circuit section is connected to the second and third nodes, and holds the data signal. The blocking section is provided between the bistable circuit and the first node, and blocks off sub-threshold leakage current.

Abstract: A semiconductor circuit includes a logic circuit section and a latch circuit section. The logic circuit section includes higher and lower potential side actual power supply lines, higher and lower potential side quasi power supply lines, a CMOS logic circuit and a power connection section. The latch circuit section includes a first CMOS inverter, a latch circuit and a transfer gate. The first CMOS inverter is connected between the higher and lower potential side quasi power supply lines. The latch circuit is operatively and selectively connected to the first CMOS inverter in series and is composed of second and third CMOS inverters connected in series. The transfer gate has the second threshold voltage and is disposed between the first CMOS inverter and the latch circuit.

Abstract: A semiconductor device having a self-test circuit which has an input signal generating circuit for generating a test signal in synchronization with a prescribed clock signal, a selector circuit for switching between a test mode for testing and a general normal mode and supplying the test signal generated by the input signal generating circuit to the tested circuit in the test mode, a divider circuit for obtaining the output signal from the tested circuit in response to the test signal, a latch circuit for well-timed extraction of the output signal of the tested circuit obtained by testing means, and a comparator for obtaining the output signal of the tested circuit from the latch circuit and comparing it with a prescribed expected value to evaluate.

Abstract: A latch circuit for eliminating slew current flowing in between power sources during period when clock signal changes. In the latch circuit, an input terminal is formed in such a way that dual transfer gates are connected to respective nodes remaining differential signal of bistable circuit which is constituted that one pair of clocked.cndot.CMOS inverter is subjected to mesh connection. An output terminal of holding signal of latch circuit is drains of PMOS and NMOS transistors being adjacent to end terminal of power source, which transistors are member of the one pair of clocked.cndot.CMOS inverter. Gates of PMOS and NMOS transistors being adjacent to side of output terminal are taken to be input terminal of gate signal of the latch circuit. During period of sampling calculation, since there exists MOS transistor which is connected in series between power sources and which is sure to stand of OFF state, it is capable of cutting transient slew current flowing between power sources.

Abstract: A semiconductor integrated circuit device has a high-speed bus driver and a bus receiver both connected to a bus line, and the high-speed bus driver enters an active mode powered from a positive power voltage line and a virtual ground line and a sleep mode isolating the virtual ground line from a ground line for reducing power consumption, wherein a switching circuit is connected between the high-speed bus driver and the bus line so as to isolate the bus line from the high-speed bus driver in transition periods and the sleep mode, thereby cutting a conductive path for through-current due to leakage current inherent in the high-speed component field effect transistors of the bus driver.

Abstract: In a semiconductor integrated logic circuit, latch circuits are provided to hold the input signal supplied to a random logic circuit just before an operation mode is switched from a normal operation mode to a test operation mode. During the test operation mode, the latched signals are continued to be supplied to random logic circuit so that the operation condition of a internal circuit of the random logic circuit is maintained as it is. Therefore, when the circuit is returned from the test operation mode to the normal operation mode, the circuit operation of the internal circuit of the random logic circuit continuing from the circuit operation in the previous normal operation condition can be obtained.