Patents by Inventor Tadahiro Matsuzaki
Tadahiro Matsuzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7981811Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.Type: GrantFiled: July 24, 2009Date of Patent: July 19, 2011Assignees: NEC Corporation, NEC LCD Technologies, LtdInventors: Shigeru Mori, Takahiro Korenari, Tadahiro Matsuzaki, Hiroshi Tanabe
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Publication number: 20090286374Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.Type: ApplicationFiled: July 24, 2009Publication date: November 19, 2009Applicants: NEC CORPORATION, NEC LCD TECHNOLOGIES, LTDInventors: Shigeru MORI, Takahiro KORENARI, Tadahiro MATSUZAKI, Hiroshi TANABE
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Patent number: 7582933Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.Type: GrantFiled: July 11, 2006Date of Patent: September 1, 2009Assignees: NEC Corporation, NEC LCD Technologies, LtdInventors: Shigeru Mori, Takahiro Korenari, Tadahiro Matsuzaki, Hiroshi Tanabe
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Patent number: 7554162Abstract: A thin film transistor substrate includes an upper electrode for electrically connecting a transparent picture element electrode to the thin film transistor. The upper electrode includes at least a first metal layer and a second metal layer formed on the first metal layer. The second metal layer has a lower reflectance than the first metal layer and the first metal layer has a region not overlapped by the second metal layer.Type: GrantFiled: June 23, 2004Date of Patent: June 30, 2009Assignee: NEC CorporationInventors: Kenichi Hayashi, Hirofumi Shimamoto, Tadahiro Matsuzaki
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Patent number: 7388625Abstract: A TFT array substrate is provided with an auxiliary capacitance that has a plurality of lower electrodes disposed for each pixel in the row and column directions below a pixel TFT and connected to the drain area of the corresponding pixel TFT. The distances L1 and L2 between separation areas formed between the lower electrodes adjacent in the row direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. The distances L3 and L4 between separation areas formed between the lower electrodes adjacent in the column direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. Furthermore, an upper electrode is disposed above the separation areas.Type: GrantFiled: December 22, 2005Date of Patent: June 17, 2008Assignee: NEC CorporationInventors: Tadahiro Matsuzaki, Kenji Sera
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Publication number: 20070012924Abstract: A base layer is formed on an insulating substrate, and a semiconductor layer is formed in localized fashion thereon. A gate insulating film is then formed so as to cover the semiconductor layer, and a gate electrode is formed on a portion of the gate insulating film. An impurity is then implanted into the semiconductor layer via the gate insulating film, and a source region, a drain region, and an LDD region are formed. The gate insulating film is etched with dilute hydrofluoric acid. An electrode-protecting insulating film is then formed so as to cover the gate electrode, and the entire surface of the surface layer portion of the electrode-protecting insulating film is etched away using dilute hydrofluoric acid. Carrier traps introduced into the electrode-protecting insulating film and the gate insulating film are thereby removed.Type: ApplicationFiled: July 11, 2006Publication date: January 18, 2007Inventors: Shigeru Mori, Takahiro Korenari, Tadahiro Matsuzaki, Hiroshi Tanabe
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Publication number: 20060132667Abstract: A TFT array substrate is provided with an auxiliary capacitance that has a plurality of lower electrodes disposed for each pixel in the row and column directions below a pixel TFT and connected to the drain area of the corresponding pixel TFT. The distances L1 and L2 between separation areas formed between the lower electrodes adjacent in the row direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. The distances L3 and L4 between separation areas formed between the lower electrodes adjacent in the column direction and the channel areas of the two pixel TFTs that correspond to the lower electrodes are substantially equal to each other. Furthermore, an upper electrode is disposed above the separation areas.Type: ApplicationFiled: December 22, 2005Publication date: June 22, 2006Inventors: Tadahiro Matsuzaki, Kenji Sera
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Publication number: 20050062042Abstract: A thin film transistor substrate includes an upper electrode for electrically connecting a transparent picture element electrode to the thin film transistor. The upper electrode includes at least a first metal layer and a second metal layer formed on the first metal layer. The second metal layer has a lower reflectance than the first metal layer and the first metal layer has a region not overlapped by the second metal layer.Type: ApplicationFiled: June 23, 2004Publication date: March 24, 2005Applicant: NEC CORPORATIONInventors: Kenichi Hayashi, Hirofumi Shimamoto, Tadahiro Matsuzaki
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Patent number: 6171163Abstract: A process for producing a field-emission cold cathode, which comprises steps of applying a protective sheet onto a wafer having a plurality of field-emitters formed at the surface and then dicing the resulting material to obtain individual devices, wherein the protective sheet is fitted to a frame for protective sheet and, in that state, is provided with preventive means for flowing adhesive, at the areas of the adhesive layer corresponding to the emitter areas, or wherein, at the time of the application of the protective sheet onto the wafer, the pressure applied to the protective sheet is reduced at the areas of the protective sheet corresponding to each emitter area, or wherein the protective sheet contains microspheres in the adhesive layer.Type: GrantFiled: October 1, 1998Date of Patent: January 9, 2001Assignee: NEC CorporationInventors: Nobuya Seko, Tadahiro Matsuzaki
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Patent number: 5965972Abstract: A field emission cold cathode comprises an n-type silicon substrate (1), a plurality of sharp-pointed emitter cones (2) formed on the n-type silicon substrate (1), and a buried insulator layer (3) formed in the n-type silicon substrate (1) to surround each of underlying regions right under each emitter cone (2). An insulator layer (4) is formed on the n-type silicon substrate (1) and has a plurality of insulator holes so as to surround each emitter cone (2). A gate electrode (5) is formed on the insulator layer (4) and has a plurality of gate holes for extracting electrons from the emitter cones (2).Type: GrantFiled: May 28, 1997Date of Patent: October 12, 1999Assignee: NEC CorporationInventors: Naruaki Takada, Yoshino Tomihari, Tadahiro Matsuzaki
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Patent number: 5629244Abstract: Using a p-type silicon substrate 1 having on its front surface an n-type silicon layer 2 with a thickness of twice or more of the desired thickness for the beam, an electrochemical etching is performed from the rear surface and the etching is stopped at the beam thickness which is twice or more of the desired thickness. Etching for the beam part 8 from the rear surface proceeds along with the etching for the gap part 9 from the front surface, and a desired thickness for the beam can be formed by completing the etching at the timing when the gap part is opened through.Type: GrantFiled: April 27, 1995Date of Patent: May 13, 1997Assignee: NEC CorporationInventor: Tadahiro Matsuzaki