Patents by Inventor Tadahiro Okamoto

Tadahiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7915538
    Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
  • Patent number: 7754534
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: July 13, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Patent number: 7723847
    Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: May 25, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Yutaka Makino, Tadahiro Okamoto, Takaki Kurita
  • Publication number: 20080261336
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Publication number: 20080124529
    Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.
    Type: Application
    Filed: January 29, 2008
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Masamitsu IKUMO, Tadahiro OKAMOTO, Eiji WATANABE
  • Patent number: 7355124
    Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: April 8, 2008
    Assignee: Fujitsu Limited
    Inventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
  • Publication number: 20080012128
    Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.
    Type: Application
    Filed: February 7, 2007
    Publication date: January 17, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yutaka Makino, Tadahiro Okamoto, Takaki Kurita
  • Publication number: 20060258045
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)?X2?(3*X¼) and (X½)?X3?(3*X¼).
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20060219429
    Abstract: A multilayer wiring board comprises a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.
    Type: Application
    Filed: July 14, 2005
    Publication date: October 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
  • Publication number: 20060214296
    Abstract: In a semiconductor-device manufacturing method, a metal bump is formed through a plurality of barrier metal layers on an opening which is selectively formed in an insulation layer covering a semiconductor substrate. The metal bump is formed on the plurality of barrier metal layers. A first etching process that selectively removes a lower metal layer among the plurality of barrier metal layers is performed by using an upper metal layer among the plurality of barrier metal layers as a mask. A reflow process that covers an end face of the lower metal layer with a metal that forms the metal bump is performed. After the lower metal layer end face is covered with the metal, a second etching process that removes a barrier metal residue on a surface of the insulation layer in a circumference of the metal bump is performed.
    Type: Application
    Filed: June 21, 2005
    Publication date: September 28, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Okamoto, Masamitsu Ikumo, Eiji Watanabe
  • Patent number: 7064436
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: June 20, 2006
    Assignee: Fujitsu Limited
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20050140004
    Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).
    Type: Application
    Filed: November 23, 2004
    Publication date: June 30, 2005
    Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
  • Publication number: 20040232549
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Application
    Filed: June 29, 2004
    Publication date: November 25, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Patent number: 6794273
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 21, 2004
    Assignee: Fujitsu Limited
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Patent number: 6680241
    Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.
    Type: Grant
    Filed: December 14, 2000
    Date of Patent: January 20, 2004
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Okamoto, Hirohisa Matsuki
  • Publication number: 20030219969
    Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.
    Type: Application
    Filed: December 31, 2002
    Publication date: November 27, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
  • Publication number: 20020014661
    Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.
    Type: Application
    Filed: December 14, 2000
    Publication date: February 7, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Okamoto, Hirohisa Matsuki
  • Patent number: 4787951
    Abstract: A method and apparatus for adhering an adhesive-backed tape or sheet to a surface of a semiconductor wafer. The apparatus comprises a housing forming a vacuum working chamber containing a supporting table for the semiconductor wafer and a plurality of rollers for exerting pressure on an adhesive-backed tape or sheet and pressing it against the wafer surface. The rollers comprise rubber rollers having different axial lengths so that, even if the wafer is warped, the tape or sheet can be uniformly adhered to the whole surface of the wafer.
    Type: Grant
    Filed: June 24, 1987
    Date of Patent: November 29, 1988
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Okamoto