Patents by Inventor Tadahiro Okamoto
Tadahiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7915538Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.Type: GrantFiled: January 29, 2008Date of Patent: March 29, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 7754534Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: GrantFiled: April 21, 2008Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 7723847Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.Type: GrantFiled: February 7, 2007Date of Patent: May 25, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Yutaka Makino, Tadahiro Okamoto, Takaki Kurita
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Publication number: 20080261336Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: April 21, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20080124529Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.Type: ApplicationFiled: January 29, 2008Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Masamitsu IKUMO, Tadahiro OKAMOTO, Eiji WATANABE
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Patent number: 7355124Abstract: A multilayer wiring board having a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.Type: GrantFiled: July 14, 2005Date of Patent: April 8, 2008Assignee: Fujitsu LimitedInventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20080012128Abstract: When a nickel (Ni) layer is formed on an electrode pad made of aluminum-silicon (Al—Si) by an electroless plating method, prior to the precipitation of zinc (Zn) which becomes a catalyst, copper (Cu) is formed in the form of discontinuous spots or islands on the surface of the electrode pad, thereby providing a copper (Cu) thin layer.Type: ApplicationFiled: February 7, 2007Publication date: January 17, 2008Applicant: FUJITSU LIMITEDInventors: Yutaka Makino, Tadahiro Okamoto, Takaki Kurita
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Publication number: 20060258045Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X½)?X2?(3*X¼) and (X½)?X3?(3*X¼).Type: ApplicationFiled: April 27, 2006Publication date: November 16, 2006Applicant: FUJITSU LIMITEDInventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
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Publication number: 20060219429Abstract: A multilayer wiring board comprises a plurality of wiring boards in which wiring layers and resin layers in each wiring board are alternately arranged in a laminated formation. In the multilayer wiring board, all the resin layers and the wiring layers, except a resin layer in the plurality of wiring boards, are separated in a same position between the plurality of wiring boards and the resin layer is continuous in the same position.Type: ApplicationFiled: July 14, 2005Publication date: October 5, 2006Applicant: FUJITSU LIMITEDInventors: Masamitsu Ikumo, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20060214296Abstract: In a semiconductor-device manufacturing method, a metal bump is formed through a plurality of barrier metal layers on an opening which is selectively formed in an insulation layer covering a semiconductor substrate. The metal bump is formed on the plurality of barrier metal layers. A first etching process that selectively removes a lower metal layer among the plurality of barrier metal layers is performed by using an upper metal layer among the plurality of barrier metal layers as a mask. A reflow process that covers an end face of the lower metal layer with a metal that forms the metal bump is performed. After the lower metal layer end face is covered with the metal, a second etching process that removes a barrier metal residue on a surface of the insulation layer in a circumference of the metal bump is performed.Type: ApplicationFiled: June 21, 2005Publication date: September 28, 2006Applicant: FUJITSU LIMITEDInventors: Tadahiro Okamoto, Masamitsu Ikumo, Eiji Watanabe
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Patent number: 7064436Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).Type: GrantFiled: November 23, 2004Date of Patent: June 20, 2006Assignee: Fujitsu LimitedInventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
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Publication number: 20050140004Abstract: A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2)?X2?(3*X1/4) and (X1/2)?X3?(3*X1/4).Type: ApplicationFiled: November 23, 2004Publication date: June 30, 2005Inventors: Masahiko Ishiguri, Hirohisa Matsuki, Hiroyuki Yoda, Tadahiro Okamoto, Masamitsu Ikumo, Shuichi Chiba
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Publication number: 20040232549Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 6794273Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: GrantFiled: December 31, 2002Date of Patent: September 21, 2004Assignee: Fujitsu LimitedInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 6680241Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.Type: GrantFiled: December 14, 2000Date of Patent: January 20, 2004Assignee: Fujitsu LimitedInventors: Tadahiro Okamoto, Hirohisa Matsuki
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Publication number: 20030219969Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: December 31, 2002Publication date: November 27, 2003Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20020014661Abstract: A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.Type: ApplicationFiled: December 14, 2000Publication date: February 7, 2002Applicant: FUJITSU LIMITEDInventors: Tadahiro Okamoto, Hirohisa Matsuki
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Patent number: 4787951Abstract: A method and apparatus for adhering an adhesive-backed tape or sheet to a surface of a semiconductor wafer. The apparatus comprises a housing forming a vacuum working chamber containing a supporting table for the semiconductor wafer and a plurality of rollers for exerting pressure on an adhesive-backed tape or sheet and pressing it against the wafer surface. The rollers comprise rubber rollers having different axial lengths so that, even if the wafer is warped, the tape or sheet can be uniformly adhered to the whole surface of the wafer.Type: GrantFiled: June 24, 1987Date of Patent: November 29, 1988Assignee: Fujitsu LimitedInventor: Tadahiro Okamoto