Abstract: A semiconductor integrated circuit formed on a chip comprises an internal circuit and an oscillating circuit, the latter generating a fundamental clock signal and a frequency divided version thereof, for operating the former in a non-testing mode of operation. A pair of first and second external connection terminals is formed on the chip and respectively connected to the input and the output of the oscillating circuit. An external oscillator is selectively connected between the pair of terminals for operating the internal circuit in a non-testing mode. A reset signal input of the internal circuit is connected to a reset external connection terminal for receiving an externally applied reset signal which resets the internal circuit.

Abstract: A semiconductor device including a plurality of CMOS (Complementary Metal Oxide Semiconductor) elements, each comprised of a conventional source region, a drain region, and a diffusion region located adjacent to source and drain elements, and each driven by a power source. A first conductor and a second conductor, which are newly introduced in the present device, are physically independent from each other. The first conductor is connected between the power source and the source region. The second conductor is connected between the power source and the diffusion region.

Abstract: A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal.

Abstract: An operational amplifier comprising a differential circuit, an output amplifier having an input terminal connected to the output terminal of the differential circuit, a phase compensating circuit, including an inverting amplifier having an input terminal connected to the output terminal of the differential circuit, and a phase compensating capacitor connected between the output terminal of the inverting amplifier and the output terminal of the differential circuit. The signal delay time of the inverting amplifier is shorter than that of the output amplifier.