Patents by Inventor Tadahiro Yoshida

Tadahiro Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8026744
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: September 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Publication number: 20100315129
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Patent number: 7816952
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Patent number: 7633287
    Abstract: A core is divided by alternately arranging plural magnetic material portions and plural non-magnetic material portions in a circumferential direction of the core through which a primary conductor penetrates. A conductor is wound around the core under conditions in which each core cross section of the core intersects the magnetic material portion and the non-magnetic material portion, each core cross section including a cut end surface of each conductor of a secondary winding wound around the core, and a ratio of a magnetic material portion cross-sectional area of the magnetic material portion to a non-magnetic material portion cross-sectional area of the non-magnetic material portion at the core cross section is kept constant at each core cross section.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: December 15, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryuichi Nishiura, Yo Makita, Hiroshi Nishizawa, Tadahiro Yoshida, Tae Hyun Kim
  • Publication number: 20090261813
    Abstract: A core is divided by alternately arranging plural magnetic material portions and plural non-magnetic material portions in a circumferential direction of the core through which a primary conductor penetrates. A conductor is wound around the core under conditions in which each core cross section of the core intersects the magnetic material portion and the non-magnetic material portion, each core cross section including a cut end surface of each conductor of a secondary winding wound around the core, and a ratio of a magnetic material portion cross-sectional area of the magnetic material portion to a non-magnetic material portion cross-sectional area of the non-magnetic material portion at the core cross section is kept constant at each core cross section.
    Type: Application
    Filed: October 22, 2008
    Publication date: October 22, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ryuichi NISHIURA, Yo Makita, Hiroshi Nishizawa, Tadahiro Yoshida, Tae Hyun Kim
  • Publication number: 20080290913
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Application
    Filed: August 1, 2008
    Publication date: November 27, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichi HASHIMOTO, Tadahiro Yoshida, Ryogo Yanagisawa
  • Patent number: 7423459
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Indutrial Co., Ltd.
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Patent number: 7321403
    Abstract: In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycle 1T), a delay of 1T is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: January 22, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryogo Yanagisawa, Tadahiro Yoshida, Satoshi Takahashi
  • Publication number: 20070061927
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Application
    Filed: November 13, 2006
    Publication date: March 15, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Patent number: 7145368
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: December 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Publication number: 20060256209
    Abstract: A dimension between ends of a magnet is set to be larger than a moving distance of a lens of a photographing optical system. The magnet is arranged such that a direction of connecting magnetic poles (S-pole and N-pole) is substantially parallel to an optical axis direction of the lens. A Hall sensor is disposed in the center of a movable range of the lens along the optical axis direction. The magnet is mounted in a lens frame such that the center of the magnet faces the Hall sensor. Lens positions and outputs of the Hall sensor can be in one-to-one correspondence with each other within the movable range of the lens. The position detecting device and the electronic apparatus are miniaturized and produced at reduced costs.
    Type: Application
    Filed: April 28, 2006
    Publication date: November 16, 2006
    Inventors: Tadahiro Yoshida, Hirotoshi Konishi, Hiroyoshi Hosota
  • Patent number: 7012447
    Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: March 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamauchi, Tadahiro Yoshida
  • Patent number: 6985007
    Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: January 10, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamauchi, Tadahiro Yoshida
  • Publication number: 20050104876
    Abstract: In a transmitting section for a video signal transmitting/receiving system for transmitting digital video signals using a plurality of transmission channels, video guard band signals are inserted into video signals associated with the transmission channels immediately before transition from a blanking region to an effective video region. In a receiving section for the system, the inserted video guard band signals are detected for the respective transmission channels. A skew among the transmission channels is detected based on the detection result. To synchronize the video guard band signals among all the transmission channels, with reference to one of the video signals associated with a transmission channel with the longest delay (i.e., delayed by one clock cycle 1T), a delay of 1T is given to the other video signals. As a result, even if a skew occurs among the transmission channels, correct pixel data is displayed.
    Type: Application
    Filed: December 23, 2004
    Publication date: May 19, 2005
    Inventors: Ryogo Yanagisawa, Tadahiro Yoshida, Satoshi Takahashi
  • Publication number: 20050012530
    Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
    Type: Application
    Filed: July 14, 2004
    Publication date: January 20, 2005
    Inventors: Shinichi Hashimoto, Tadahiro Yoshida, Ryogo Yanagisawa
  • Publication number: 20040165668
    Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 26, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroyuki YAMAUCHI, Tadahiro YOSHIDA
  • Publication number: 20040161042
    Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data line; and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
    Type: Application
    Filed: February 18, 2004
    Publication date: August 19, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroyuki YAMAUCHI, Tadahiro YOSHIDA
  • Patent number: 6768334
    Abstract: A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data lines and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: July 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Yamauchi, Tadahiro Yoshida
  • Patent number: 6633588
    Abstract: First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: October 14, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadahiro Yoshida, Hiroyuki Yamauchi, Hironori Akamatsu, Satoshi Takahashi, Yutaka Terada, Yukio Arima, Takashi Hirata, Yoshihide Komatsu
  • Patent number: 6631486
    Abstract: A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: October 7, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihide Komatsu, Tadahiro Yoshida, Yukio Arima