Patents by Inventor Tadahisa Kohyama

Tadahisa Kohyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110069683
    Abstract: One object of the present invention is to prevent deterioration of communication quality and perform handover while maintaining a stable communication state. The terminal detection unit classifies a terminal device 20 into a predetermined moving object group based on determination factors. The time slot specifying unit 1051 associates a moving object group to a time slot and specifies the associated time slot for the terminal device 20 of the moving object group. The channel allocation unit 1052 allocates a sub-channel block included in the time slot specified by the time slot specifying unit 1051 to the terminal device 20 of the moving object group.
    Type: Application
    Filed: March 27, 2009
    Publication date: March 24, 2011
    Applicant: KYOCERA CORPORATION
    Inventor: Tadahisa Kohyama
  • Patent number: 7688886
    Abstract: The power consumption of a receiving apparatus is reduced. A first equalization unit receives the input of digital signals and then performs equalization processing on them so as to output first equalizer output signals. A first selector selects either the digital signals or the first equalizer output signals, and outputs the selected signals to an despread unit or a second equalization unit. The despread unit carries out an despread, and an PSK demodulation unit demodulates the despread signal by PSK. The second equalization unit performs equalization processing, and a CCK demodulation unit performs CCK demodulation. A second selector operates in response to the second selector. A modulation scheme determining unit extracts information on a modulation scheme in use, from the signal demodulated by the PSK demodulation unit so as to decide on the modulation scheme. Based on the modulation scheme determined, a decision unit specifies the selection of signals at the first selector and the second selector.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: March 30, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tadahisa Kohyama
  • Publication number: 20080037622
    Abstract: The power consumption of a receiving apparatus is reduced. A first equalization unit receives the input of digital signals and then performs equalization processing on them so as to output first equalizer output signals. A first selector selects either the digital signals or the first equalizer output signals, and outputs the selected signals to an despread unit or a second equalization unit. The despread unit carries out an despread, and an PSK demodulation unit demodulates the despread signal by PSK. The second equalization unit performs equalization processing, and a CCK demodulation unit performs CCK demodulation. A second selector operates in response to the second selector. A modulation scheme determining unit extracts information on a modulation scheme in use, from the signal demodulated by the PSK demodulation unit so as to decide on the modulation scheme. Based on the modulation scheme determined, a decision unit specifies the selection of signals at the first selector and the second selector.
    Type: Application
    Filed: February 10, 2005
    Publication date: February 14, 2008
    Inventor: Tadahisa Kohyama
  • Publication number: 20050220186
    Abstract: A delay unit comprises a plurality of taps for sequentially delaying an input digital received signal. A shift unit changes combinations of a plurality of digital received signals delayed by the delay unit and a multiplier unit. A coefficient retaining unit manages a plurality of coefficients to be multiplied by the plurality of digital received signals delayed by the delay unit. A selector unit 352 selects one of the coefficients retained in the coefficient retaining unit in accordance with an instruction from a control unit. The multiplier unit multiplies the plurality of digital received signals delayed by the delay unit by the coefficient selected by the selector unit. An adder adds up results of multiplication by the multiplier unit and outputs a result of addition as a filter output signal.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 6, 2005
    Inventor: Tadahisa Kohyama