Patents by Inventor Tadahito Miura

Tadahito Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data buffering based on priority tagging of input data
    Patent number: 8122169
    Abstract: A data buffer device includes: a tag value generation circuit that generates a tag value; a first buffer that stores first priority data; a second buffer that stores second priority data; and a data output circuit that outputs the first priority data or the second priority data, wherein the tag value generation circuit sets a tag value for the following second input data to a second tag value which differs from a first tag value for second preceding input data, and sets a tag value of the following first input data to a fourth tag value that is the same as a third tag value for the first preceding input data, and wherein the data output circuit outputs the first priority data or the second priority data in a first mode based on the tag values and outputs the first priority data earlier in a second mode.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Ryuji Kojima, Tadahito Miura, Yoshikazu Tsuzuki, Shinichirou Nakajima, Daishi Kawabata, Hiroki Abukawa
  • DATA BUFFER DEVICE
    Publication number: 20100281193
    Abstract: A data buffer device includes: a tag value generation circuit that generates a tag value; a first buffer that stores first priority data; a second buffer that stores second priority data; and a data output circuit that outputs the first priority data or the second priority data, wherein the tag value generation circuit sets a tag value for the following second input data to a second tag value which differs from a first tag value for second preceding input data, and sets a tag value of the following first input data to a fourth tag value that is the same as a third tag value for the first preceding input data, and wherein the data output circuit outputs the first priority data or the second priority data in a first mode based on the tag values and outputs the first priority data earlier in a second mode.
    Type: Application
    Filed: April 27, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Ryuji KOJIMA, Tadahito Miura, Yoshikazu Tsuzuki, Shinichirou Nakajima, Daishi Kawabata, Hiroki Abukawa
  • Clock signal generation circuit and audio data processing apparatus
    Patent number: 6825705
    Abstract: A clock generation apparatus includes a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: November 30, 2004
    Assignee: Fujitsu Limited
    Inventors: Akio Kato, Masami Iwamoto, Hirokazu Asami, Tadahito Miura
  • Clock signal generation circuit and audio data processing apparatus
    Publication number: 20030234672
    Abstract: A clock generation apparatus includes a first clock generation circuit which generates a clock signal by making state transition in synchronization with a master clock signal after exiting from a predetermined state in response to a timing signal supplied from an exterior of the apparatus, a counter which counts clock pulses of the master clock signal after exiting from a reset state in response to the timing signal, and a reset circuit which resets the counter and sets the first clock generation circuit in the predetermined state in response to the count of the counter reaching a first predetermined value.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 25, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Akio Kato, Masami Iwamoto, Hirokazu Asami, Tadahito Miura