Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.

Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.

Abstract: A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.

Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.

Abstract: A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.

Abstract: A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.

Abstract: A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.

Abstract: A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.