Patents by Inventor Tadamasa Murakami
Tadamasa Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11344206Abstract: An electronic device is provided. The electronic device includes an earphone including a first impedance component, a signal generator configured to output a first alternating current (AC) signal, a first circuit including at least one first analog device having an impedance component electrically coupled to the first impedance component, and configured to receive the first AC signal and output a first detection signal including a voltage component corresponding to the first impedance component, and at least one processor configured to generate at least one piece of biometric information, based on the first detection signal, and output the at least one piece of biometric information.Type: GrantFiled: December 13, 2019Date of Patent: May 31, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Atsuya Yokoi, Tadamasa Murakami, Toshihiro Kitajima, Edwardo Murakami
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Patent number: 11043919Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.Type: GrantFiled: July 26, 2019Date of Patent: June 22, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Toshihiko Yoshimasu, Tadamasa Murakami, Tsuyoshi Sugiura
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Publication number: 20200187795Abstract: An electronic device is provided. The electronic device includes an earphone including a first impedance component, a signal generator configured to output a first alternating current (AC) signal, a first circuit including at least one first analog device having an impedance component electrically coupled to the first impedance component, and configured to receive the first AC signal and output a first detection signal including a voltage component corresponding to the first impedance component, and at least one processor configured to generate at least one piece of biometric information, based on the first detection signal, and output the at least one piece of biometric information.Type: ApplicationFiled: December 13, 2019Publication date: June 18, 2020Inventors: Atsuya YOKOI, Tadamasa MURAKAMI, Toshihiro KITAJIMA, Edwardo MURAKAMI
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Publication number: 20200036340Abstract: A power amplifier includes a first bias circuit including a first and third transistor, a first sub-bias circuit, and an amplifying circuit including a fourth transistor. In the first bias circuit, a second terminal of the first transistor and a second terminal of the first sub-bias circuit are grounded, a control terminal of the first transistor is connected to a control terminal of the first sub-bias circuit, a first terminal of the first sub-bias circuit is connected to a constant voltage terminal, a first terminal of the first transistor is connected to a second terminal of the third transistor, a first terminal of the third transistor is connected to a control terminal of the third transistor. The amplifying circuit amplifies an input signal power based on a first bias signal from the first bias circuit to a control terminal of the fourth transistor.Type: ApplicationFiled: July 26, 2019Publication date: January 30, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Toshihiko Yoshimasu, Tadamasa Murakami, Tsuyoshi Sugiura
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Publication number: 20180152154Abstract: A radio frequency power amplifier includes: a transistor configured to amplify a signal at a selected signal frequency; a first line connected to an output of the transistor and disposed on a printed circuit board; and a second line and a third line branched from a rear stage of the first line and disposed on the printed circuit board. The second line is configured to set impedance for the selected signal frequency or a double-wave frequency of the selected signal frequency.Type: ApplicationFiled: November 28, 2017Publication date: May 31, 2018Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Tadamasa MURAKAMI, Tsuyoshi SUGIURA, Koki TANJI, Norihisa OTANI, Satoshi FURUTA
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Patent number: 9230955Abstract: An element can be prevented from being damaged even when a high level signal is input to an integrated circuit having a variable capacitance element whose capacitance is variable by digital signal control. There is provided an integrated circuit including b sub-circuits (b is an integer equal to or greater than 1) that are connected in series between a first terminal and a second terminal and have capacitance 2b-1 times larger than predetermined unit capacitance. The b-th sub-circuit includes 2b-1 configurations, which are connected in parallel, each including at least two capacitors connected in series and at least two stacked switch elements. At least the two stacked switch elements are operated to all switched for each sub-circuit, and at least one switch element of at least the two stacked switch elements is provided between at least the two capacitors.Type: GrantFiled: March 15, 2013Date of Patent: January 5, 2016Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Tadamasa Murakami
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Publication number: 20150194937Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventor: Tadamasa MURAKAMI
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Patent number: 8994454Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.Type: GrantFiled: September 12, 2012Date of Patent: March 31, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Tadamasa Murakami
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Patent number: 8836429Abstract: There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.Type: GrantFiled: September 12, 2012Date of Patent: September 16, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Tadamasa Murakami
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Patent number: 8791756Abstract: The amplifying circuit includes: an input transistor having a gate electrode connected to a signal input terminal inputting a wireless signal, a drain electrode connected to a power supply terminal, and a source electrode connected to a ground terminal; a first switch installed between the signal input terminal and the gate electrode; and a second switch installed between the power supply terminal and the drain electrode, wherein the input transistor has a predetermined bias voltage applied to the gate electrode thereof to simultaneously turn the first and second switches on during reception of the wireless signal and simultaneously turn the first and second switches off while applying the predetermined bias voltage to the gate electrode during transmission of the wireless signal.Type: GrantFiled: September 11, 2012Date of Patent: July 29, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Tadamasa Murakami
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Publication number: 20130241033Abstract: An element can be prevented from being damaged even when a high level signal is input to an integrated circuit having a variable capacitance element whose capacitance is variable by digital signal control. There is provided an integrated circuit including b sub-circuits (b is an integer equal to or greater than 1) that are connected in series between a first terminal and a second terminal and have capacitance 2b-1 times larger than predetermined unit capacitance. The b-th sub-circuit includes 2b-1 configurations, which are connected in parallel, each including at least two capacitors connected in series and at least two stacked switch elements. At least the two stacked switch elements are operated to all switched for each sub-circuit, and at least one switch element of at least the two stacked switch elements is provided between at least the two capacitors.Type: ApplicationFiled: March 15, 2013Publication date: September 19, 2013Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Tadamasa MURAKAMI
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Publication number: 20130128779Abstract: The amplifying circuit includes: an input transistor having a gate electrode connected to a signal input terminal inputting a wireless signal, a drain electrode connected to a power supply terminal, and a source electrode connected to a ground terminal; a first switch installed between the signal input terminal and the gate electrode; and a second switch installed between the power supply terminal and the drain electrode, wherein the input transistor has a predetermined bias voltage applied to the gate electrode thereof to simultaneously turn the first and second switches on during reception of the wireless signal and simultaneously turn the first and second switches off while applying the predetermined bias voltage to the gate electrode during transmission of the wireless signal.Type: ApplicationFiled: September 11, 2012Publication date: May 23, 2013Inventor: Tadamasa MURAKAMI
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Publication number: 20130127538Abstract: There is provided a CMOS integrated circuit suppressing gate resistance and preventing increase in noise figure (NF), while an input transistor has a comb structure. The transistor includes: a gate electrode extended from a gate wiring to form a comb shape and receiving an input signal from an input terminal; a source electrode extended from a source wiring facing the gate wiring to form a comb shape and connected to a ground terminal, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode; a drain electrode extended from a drain wiring facing the gate wiring to form a comb shape, comb teeth thereof being interposed in every other space between comb teeth of the gate electrode where the comb teeth of the source electrode are absent, wherein an overlapping region between the gate electrode and the source electrode or the drain electrode is absent.Type: ApplicationFiled: September 12, 2012Publication date: May 23, 2013Inventor: Tadamasa MURAKAMI
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Publication number: 20130127544Abstract: According to embodiments of the present invention, an over-input signal may be limited to be within a range between adjustable upper limit voltage and lower limit voltage while suppressing deterioration of a noise figure. An amplifier circuit includes an input transistor; an input transistor; a resistor element having a first terminal connected to a gate of the input transistor and a second terminal connected to a bias voltage; and a protective circuit connected to the gate of the input transistor and limiting an input to the gate of the input transistor to be within a range between an upper limit voltage and lower limit voltage adjustable based on the bias voltage.Type: ApplicationFiled: September 12, 2012Publication date: May 23, 2013Inventor: Tadamasa MURAKAMI
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Publication number: 20130127539Abstract: There is provided a CMOS integrated circuit capable of avoiding deterioration of NF characteristic and achieving a high degree of linearity in the case in which an LNA circuit is formed on an SOI substrate and an LAN circuit is formed in a bulk CMOS process. The CMOS integrated circuit includes a field effect transistor having a gate electrode connected to a signal input terminal, a drain electrode connected to a power terminal, and a source electrode connected to a ground terminal, wherein the field effect transistor is formed on the SOI substrate and a connection between a body potential and a potential lower than a source potential are formed by a resistor element. The deterioration of NF characteristic can be avoided and a high degree of linearity can be achieved by using this CMOS integrated circuit.Type: ApplicationFiled: September 12, 2012Publication date: May 23, 2013Inventor: Tadamasa MURAKAMI
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Patent number: 8072268Abstract: An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines.Type: GrantFiled: January 11, 2010Date of Patent: December 6, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Tadamasa Murakami
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Publication number: 20100182088Abstract: An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines.Type: ApplicationFiled: January 11, 2010Publication date: July 22, 2010Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Tadamasa Murakami
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Patent number: 7570715Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.Type: GrantFiled: November 18, 2005Date of Patent: August 4, 2009Assignee: Oki Semiconductor Co., Ltd.Inventors: Sunao Mizunaga, Tadamasa Murakami
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Patent number: 7317358Abstract: The present invention provides a differential amplifier circuit wherein the center voltages of outputs are not affected by a variation in source potential. A node located in the middle point of a resistor connected between complementary output nodes of an amplifying unit is connected to a positive phase input terminal of an operational amplifier. An antiphase input terminal of the operational amplifier is supplied with a reference voltage. The output of the operational amplifier is supplied in common to the gates of load PMOSs connected between a source potential and the two output nodes as a control voltage. Owing to such a feedback circuit, the potential of the node reaches the reference voltage, and the center voltages of complementary output signals are not affected by the source potential and are controlled so as to always take the reference voltage.Type: GrantFiled: September 21, 2004Date of Patent: January 8, 2008Assignee: Oki Electric Industry Co., Ltd.Inventor: Tadamasa Murakami
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Patent number: 7233175Abstract: An amplitude limiting value can be set to an intended value of a designer and the dependence of the amplitude limiting value on the temperature can be avoided.Type: GrantFiled: September 21, 2004Date of Patent: June 19, 2007Assignee: Oki Electric Industry Co., Ltd.Inventor: Tadamasa Murakami