Patents by Inventor Tadami Yasuda

Tadami Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7236703
    Abstract: As is described above, an optical wavelength division multiplexing and transmission apparatus according to the present invention has the configuration in which a plurality of slave racks coupling to a master rack can be additionally installed one after another with the master rack. Therefore, in cases where it is desired to expand a function of a transmitter and a function of a receiver due to the increase of a quality of information to be transmitted, the additional installation of the slave rack can be performed without exerting influence on a communication means installed in advance and currently used. Accordingly, it can be expected that the optical wavelength division multiplexing and transmission apparatus is adapted for the optical communication service which is more and more increased in the future.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: June 26, 2007
    Assignees: Mitsubishi Denki Kabushiki Kaisha, KDDI Submarine Cable Systems Inc.
    Inventors: Shigeo Yamanaka, Takashi Mizuochi, Katsuhiro Shimizu, Koji Goto, Shinichi Nakagawa, Eiichi Shibano, Tadami Yasuda
  • Patent number: 6870859
    Abstract: A multiplex transmission system of tributary signals multiplexes a plurality of tributary signals after adding to them frame information common to all the tributary signals and identification codes different for the individual tributary signals. This makes it possible to solve a problem of a conventional multiplex system of tributary signals in that the transmission rate is limited because it multiplexes a plurality of tributary signals with adding an SOH (section overhead) to generate an STM-N frame to be transmitted and received, which requires a considerable time.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: March 22, 2005
    Assignees: KDD Corporation, KDD Submarine Cable Systems, Inc., Mitsubishi Denki Kabushiki Kaisha
    Inventors: Seiji Kozaki, Kazuo Kubo, Hiroshi Ichibangase, Eiichi Shibano, Tadami Yasuda
  • Patent number: 6868514
    Abstract: In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is returned to the original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct errors in the information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct residual errors in the information, and the order is returned to the original order by a second deinterleaving circuit 37.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: March 15, 2005
    Assignees: Mitsubishi Denki Kabushiki Kaisha, KDD Submarine Cable Systems Inc.
    Inventors: Kazuo Kubo, Hideo Yoshida, Hiroshi Ichibangase, Hidenori Taga, Eiichi Shibano, Tadami Yasuda
  • Publication number: 20020129313
    Abstract: In an FEC frame structuring method, and an FEC multiplexer, the order of information is changed by a first interleaving circuit 32, a first error correction code is generated by an RS (239, 223) coding circuit 33, the order is rechanged to an original order by a first deinterleaving circuit 34, and a second error correction code is generated by an RS (255, 239) coding means 5. The second error correction code is decoded by an RS (255, 239) decoding circuit 11 to correct an error of information, the order of information is changed by a second interleaving circuit 35, the first error correction code is decoded by an RS (239, 223) decoding circuit 36 to correct a residual error of information, and the order is rechanged to an original order by a second interleaving circuit 37.
    Type: Application
    Filed: October 9, 2001
    Publication date: September 12, 2002
    Inventors: Kazuo Kubo, Hideo Yoshida, Hiroshi Ichibangase, Hidenori Taga, Eiichi Shibano, Tadami Yasuda