Abstract: A digital transmission system includes at least a client device and a transmission device, and rate-adjusts the client signal transmitted from the client device to the transmission device before accommodating/multiplexing the signal in a frame. The transmission device includes a rate adjusting unit and a frame processing unit. The rate adjusting unit encapsulates the client signal by using a predetermined frame structure, inserts an idle pattern if necessary, and performs rate adjustment into the bit rate which can be contained in the frame. The frame processing unit accommodates/multiplexes the signal after the rate adjustment. The digital transmission system inserts a bit string of the client signal directly in a payload area of the digital frame, or accommodates and multiplexes it. Alternatively, a specific pattern is accommodated in the payload area, or accommodated and multiplexed after performing a reversible digital signal processing.

Abstract: According to the present invention, as shown in FIG. 5(a), when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED as shown in FIG. 5(c) when a stuff pulse in the line data is detected as indicated by the symbol m0 in FIG. 5(b), thereby generating the signal for clock recovery ED.

Abstract: A signal generating method and circuit for reducing jitters occurring in a recovered clock signal CK since even when multiple items of specific data are inserted in one cycle of generation period for an enable period, a deviation of an output cycle of the enable period can be eliminated. Accordingly, when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED when a stuff pulse in the line data is detected as indicated by the symbol m0, thereby generating the signal for clock recovery ED.

Abstract: A digital transmission system includes at least a client device and a transmission device, and rate-adjusts the client signal transmitted from the client device to the transmission device before accommodating/multiplexing the signal in a frame. The transmission device includes a rate adjusting unit and a frame processing unit. The rate adjusting unit encapsulates the client signal by using a predetermined frame structure, inserts an idle pattern if necessary, and performs rate adjustment into the bit rate which can be contained in the frame. The frame processing unit accommodates/multiplexes the signal after the rate adjustment. The digital transmission system inserts a bit string of the client signal directly in a payload area of the digital frame, or accommodates and multiplexes it. Alternatively, a specific pattern is accommodated in the payload area, or accommodated and multiplexed after performing a reversible digital signal processing.

Abstract: In an information memory device of the type wherein informations are sequentially stored in cells of a memory cell array and read out from the cells according to selected addresses, there are provided an internal address generator for generating an internal address, an address information selector for selecting either one of the internal address and an external address supplied from outside to form a selected address, and an information memory circuit for storing a memory information at a position designated by the selected address and for reading out the information stored in the designated position.

Abstract: There are provided first and second units each comprising first and second serially connected registers receiving inputs at different timings and a switch connected on the output side of the second register. The output sides of the switches of the first and second units are commonly connected together to form a pair, and a plurality of pairs are arranged in the form of a tree. Control signals having different control timings of the switches are sequentially applied to respective switches of each stage at a predetermined time spacing. The first register of the first stage constitutes a portion of data receiving means, and sequentially stores sequentially given data at a first timing. The second registers of the first stage are supplied with a common frame pulse to take in contents of respective first registers, while the first registers of the second and following stages sequentially store data at a third timing synchronous with but different from the second time.

Abstract: A time-switch circuit for use in a primary time switch (PTSW), a secondary time switch (STSW), and a space switch (SSW) of a digital time-division switching system is disclosed. The time switch comprises a plurality of memory circuits (MUC.sub.11 to MUC.sub.15, MUC.sub.21 to MUC.sub.25). Each memory circuit comprises a memory unit (MEM), an address buffer (AB) for a first address, an m-ary counter (T-CTR) for a second address, an address selector (AS) for selecting either the first or second address, an input data buffer (IB), and an output data buffer (OB). In a write cycle, input data from the input data buffer is written into the memory unit by either the first or second address signal, and in a read cycle, output data is read out of the memory unit by either the second or first address. Selection of the first and second addresses is performed by the address selector, which is controlled by an address-selection mode switch circuit (M.sub.0).