Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.

Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.

Abstract: If a stereoscopic display mode is selected, the angle of view of each of a pair of perspective-projection virtual cameras and a distance between the perspective-projection virtual cameras are determined based on an output signal from a 3D adjustment switch. Based on these perspective-projection virtual cameras, an image for right eye and an image for left eye are rendered, and a stereoscopically visible image is generated based on these images. If a planar display mode is selected, a single orthogonal-projection virtual camera is used to generate a planarly visible image.

Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract: A stacked-type semiconductor device includes a plurality of semiconductor elements stacked on a wiring board. Electrode pads of these semiconductor elements are electrically connected to connection pads of the wiring board via metal wires respectively. The long-looped metal wires connected to the upper semiconductor element are fixed by a wire fixing resin portion to the short-looped metal wires connected to the lower semiconductor element. The wire fixing resin portion is filled at least between the metal wires. The stacked semiconductor elements are sealed by a sealing resin layer together with the metal wires.

Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.

Abstract: A substrate having an element mounting portion is placed on a suction stage having a suction hole. The suction hole is provided so as to suck a region excluding the element mounting portion of the substrate. Otherwise, the suction hole has a hole size of not less than 0.5 mm nor more than 1.0 mm. A fist semiconduct or substrate is sucked with a suction rubber collet with Shore A hardness of not less than 50 nor more than 70. The first semiconductor element is bonded to the element mounting portion of the substrate. A second semiconductor element having an adhesive layer with a remaining volatile content of 0.5% or less is disposed on the first semiconductor substrate. The adhesive layer is heated to a temperature in a range of not less than 120° C. nor more than 150° C. and bonded.

Abstract: A primary thin hard coating selected from chrome nitride, titanium nitride and titanium carbide, and a secondary thin coating selected from elemental metals and their corresponding alloys capable of dry-plating are provided on a metal material by an ion-plating technique. The secondary thin coating is provided by ion-plating in the absence of an inert gas, such as argon or helium, which is different from conventional methods for ion-plating the elemental metal in the presence of such inert gas.