Patents by Inventor Tadanori Segawa
Tadanori Segawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535106Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.Type: GrantFiled: January 24, 2007Date of Patent: May 19, 2009Assignee: Renesas Technology Corp.Inventors: Osamu Shiono, Takao Ishikawa, Takashi Namekawa, Yasutaka Suzuki, Takashi Naito, Hiroki Yamamoto, Daigorou Kamoto, Ken Takahashi, Tadanori Segawa, Toshiya Satoh, Takao Miwa, Shigehisa Motowaki
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Patent number: 7378333Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.Type: GrantFiled: June 29, 2005Date of Patent: May 27, 2008Assignee: Renesas Technology Corp.Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Publication number: 20070114653Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.Type: ApplicationFiled: January 24, 2007Publication date: May 24, 2007Applicants: Hitachi, Ltd., Renesas Technology Corp.Inventors: Osamu Shiono, Takao Ishikawa, Takashi Namekawa, Yasutaka Suzuki, Takashi Naito, Hiroki Yamamoto, Daigoro Kamoto, Ken Takahashi, Tadanori Segawa, Toshiya Sato, Takao Miwa, Shigehisa Motowaki
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Patent number: 7217992Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.Type: GrantFiled: June 7, 2004Date of Patent: May 15, 2007Assignee: Renesas Technology Corp.Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
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Patent number: 7183650Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.Type: GrantFiled: July 12, 2002Date of Patent: February 27, 2007Assignee: Renesas Technology Corp.Inventors: Osamu Shiono, Takao Ishikawa, Takashi Namekawa, Yasutaka Suzuki, Takashi Naito, Hiroki Yamamoto, Daigoro Kamoto, Ken Takahashi, Tadanori Segawa, Toshiya Sato, Takao Miwa, Shigehisa Motowaki
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Publication number: 20050245061Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.Type: ApplicationFiled: June 29, 2005Publication date: November 3, 2005Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Patent number: 6946723Abstract: A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.Type: GrantFiled: March 16, 2001Date of Patent: September 20, 2005Assignee: Renesas Technology Corp.Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Patent number: 6888230Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.Type: GrantFiled: October 28, 1999Date of Patent: May 3, 2005Assignee: Renesas Technology Corp.Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
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Publication number: 20040217453Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.Type: ApplicationFiled: June 7, 2004Publication date: November 4, 2004Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
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Publication number: 20040217455Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.Type: ApplicationFiled: January 9, 2004Publication date: November 4, 2004Inventors: Osamu Shiono, Takao Ishikawa, Takashi Namekawa, Yasutaka Suzuki, Takashi Naito, Hiroki Yamamoto, Daigoro Kamoto, Ken Takahashi, Tadanori Segawa, Toshiya Sato, Takao Miwa, Shigehisa Motowaki
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Patent number: 6621154Abstract: A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25° C. and a carboxyl group.Type: GrantFiled: September 28, 2000Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Takao Miwa, Akira Nagai, Akihiro Yaguchi, Ichiro Anjo, Asao Nishimura
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Publication number: 20020025655Abstract: The present invention is a semiconductor device having the semiconductor element 1 obtained by cutting a semiconductor wafer with the electrode pad 2 formed on one side along the scribe line, the semiconductor element protective layer 7 on the semiconductor element 1 which has the opening 7(1) on the pad 2, the stress cushioning layer 3 on the layer 7 which has the opening 3(1) on the pad 2, the lead wire portion 4 reaching the layer 3 from the electrode pad 2 via the openings 7(1) and 3(1), the external electrodes 6 on the lead wire portion 4, and the conductor protective layer 5 on the layer 3 and the layer 7, the layer 3, and the conductor protective layer 5 form the respective end faces on the end surface 1(1) of the semiconductor element 1 inside the scribe line and expose the range from the end face of the end surface 1(1) to the inside of the scribe line.Type: ApplicationFiled: March 16, 2001Publication date: February 28, 2002Inventors: Toshiya Satoh, Masahiko Ogino, Tadanori Segawa, Yoshihide Yamaguchi, Hiroyuki Tenmei, Atsushi Kazama, Ichiro Anjo, Asao Nishimura
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Patent number: 6348741Abstract: A manufacturing method makes it possible to produce a semiconductor apparatus which is outstanding in mounting reliability at a high manufacturing yield rate. A semiconductor apparatus, in which, on the surface of a semiconductor chip with a circuit and an electrode formed thereon, a stress cushioning layer is provided, except for a part where the electrode is, has a wiring layer connected to the electrode on the stress cushioning layer, an external protection film on the wiring layer and stress cushioning layer, a window where a part of the wiring layer is exposed at a predetermined location of the external protection film, and an external electrode which is electrically connected to the wiring layer via the window. The stress cushioning layer, wiring layer, conductor, external protection film, and external electrode are formed on the inside of the end of the semiconductor chip.Type: GrantFiled: September 29, 2000Date of Patent: February 19, 2002Assignee: Hitachi, Ltd.Inventors: Masahiko Ogino, Takao Miwa, Toshiya Satoh, Akira Nagai, Tadanori Segawa, Akihiro Yaguchi, Ichiro Anjo, Asao Nishimura, Takumi Ueno
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Patent number: 4965657Abstract: A resin encapsulated semiconductor device sealed with an epoxy resin molding material particularly containing a brominated epoxy resin as a flame retardant with the bromine content of 0.5% by weight or less, antimony oxide as a flame retardant in an amount of 2.0% by weight or more and a quaternary phosphonium tetrasubstituted borate as a curing accelerator is excellent in connection reliability at Au/Al junctions and heat resistance.Type: GrantFiled: August 2, 1988Date of Patent: October 23, 1990Assignees: Hitachi Ltd., Hitachi Chemical Co., Ltd.Inventors: Masatsugu Ogata, Tadanori Segawa, Hidetoshi Abe, Shigeo Suzuki, Tatsuo Kawata
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Patent number: 4933744Abstract: Resin encapsulated electronic devices are provided by encapsulating so-called flat-shaped, plate-like, or angular-shaped electronic devices with a resin composition containing rubber-like particles preferably having an average particle size of 150 .mu.m or less. In the course of production of said resin encapsulated electronic devices, no crack is produced in the electronic devices by the stress from the outside, and after production, said resin encapsulated electronic devices are amazingly lessened in formation of cracks by thermal stress and have high reliability.Type: GrantFiled: February 1, 1988Date of Patent: June 12, 1990Assignee: Hitachi, Ltd.Inventors: Tadanori Segawa, Hiroshi Suzuki, Masahiro Kitamura, Shunichi Numata, Kunihiko Nishi