Patents by Inventor Tadao Akamine

Tadao Akamine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7868907
    Abstract: A thermal head driving IC for supplying voltage to a plurality of heating resistors each controlled by a driving MOS transistor includes a switch for making and breaking electrically between a substrate and a source of the plurality of driving MOS transistors. In a case where the plurality of heating resistors are activated, the plurality of driving MOS transistors are turned on and the switch is turned off, whereby the substrate potential is floated. As a result, the substrate potential is forward-biased against the source by a substrate current generated in a high-electric-field depletion region near the drain, and a parasitic bipolar transistor turns on, whereby both the plurality of driving MOS transistors and the parasitic bipolar transistor turn on. In a case where the plurality of heating resistors are not activated, a signal for turning off the plurality of driving NMOS transistors is given, and the switch is turned on.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: January 11, 2011
    Assignee: Seiko Instruments Inc.
    Inventors: Tadao Akamine, Toshihiko Omi
  • Publication number: 20080180512
    Abstract: Provided is a thermal head driving IC for supplying voltage to a plurality of heating resistors each controlled by a driving MOS transistor, including a switch for making and breaking between a substrate and a source of the plurality of driving MOS transistors. In a case where the plurality of heating resistors are activated, the plurality of driving MOS transistors are turned on and the switch is turned off, a substrate is floated. As a result, a substrate potential is forward-biased against the source by a substrate current generated in a high-electric-field depletion region near the drain, and a parasitic bipolar transistor turns on, whereby both the plurality of driving MOS transistors and the parasitic bipolar transistor turn on. In a case where the plurality of heating resistors are not activated, a signal for turning off the plurality of driving NMOS transistors is given, and the switch is turned on.
    Type: Application
    Filed: January 24, 2008
    Publication date: July 31, 2008
    Inventors: Tadao Akamine, Toshihiko Omi
  • Patent number: 6469405
    Abstract: A constant-current FET functions as a constant current element by application of a constant voltage to the gate thereof. A first switch FET is disposed between the constant-current FET and a power supply without another switching element being disposed between the constant current FET and an output terminal. A second switch FET that performs an on/off operation in association with an on/off operation performed by the first switch FET is connected between the output terminal and ground.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: October 22, 2002
    Assignee: Seiko Instruments Inc.
    Inventors: Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo, Tadao Akamine
  • Patent number: 5925574
    Abstract: A method of producing a bipolar transistor composed of collector, base and emitter regions disposed sequentially on a semiconductor substrate. According to the method, a semiconductor layer is deposited on the collector region, the semiconductor layer is cleaned to expose an active surface, an impurity source gas is applied to the exposed active surface while heating the substrate to form an impurity adsorption layer, the impurity is diffused into the semiconductor layer to form the base region, another semiconductor layer is deposited on the base region, this semiconductor layer is cleaned to expose an active surface, another impurity source gas is applied to the exposed active surface while heating the substrate to form another impurity adsorption layer, and impurity is diffused into the semiconductor layer to from the impurity adsorption layer to form the emitter region.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: July 20, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Yoshikazu Kojima
  • Patent number: 5874352
    Abstract: A method of producing an MIS transistor by preparing a substrate formed with a gate electrode and a semiconductor layer which defines a source region and a drain region, removing a natural oxide film from a surface of the gate electrode and from a surface of the semiconductor layer to expose an active surface, delivering a source gas containing an impurity component to the exposed active surface to deposit thereon an impurity adsorption film, and annealing the substrate to diffuse the impurity component from the impurity adsorption film into the gate electrode and concurrently into the semiconductor layer to form the source and drain regions. The gate electrode has the same conductivity type as the source and drain regions.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: February 23, 1999
    Assignee: Sieko Instruments Inc.
    Inventors: Tadao Akamine, Kenji Aoki
  • Patent number: 5763903
    Abstract: An avalanche photodiode for detecting x-rays and other radiation comprises a first substrate having a portion removed therefrom, a first insulating film formed on the first substrate, a second substrate comprising a floating zone silicon semiconductor substrate disposed on the first insulating film, an impurity region selectively formed in the second substrate at a surface corresponding to the removed portion, a PN junction formed on the second substrate, a glass substrate mounted to the second substrate, a first electrode formed on the first substrate for applying a voltage to the impurity region, a second electrode formed on the second substrate for applying a voltage to the second substrate, a third electrode formed on the glass substrate and electrically connected to the second electrode, and an integrated circuit package having a lead pin connected to the third electrode. Accordingly, a shallow depletion layer may be provided on a floating zone SOI substrate.
    Type: Grant
    Filed: August 17, 1995
    Date of Patent: June 9, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Masaaki Mandai, Tomoyuki Yoshino, Tadao Akamine, Yutaka Saitoh, Junko Yamanaka, Osamu Koseki
  • Patent number: 5753530
    Abstract: A solid phase diffusion process using boron silicide film as diffusion source to improve controllability of diffusion of boron impurity into a silicon substrate in order to achieve a shallow junction. The process includes: cleaning the surface of a Si substrate by removing the native oxide film thereof to expose an active surface; treating the active surface to form thereon a boron silicide film as an impurity source; and introducing boron impurity from the boron silicide film into the Si substrate to form a boron diffusion layer. In this manner, a boron diffusion layer having a high surface concentration and a shallow junction can be formed because the boron silicide film is formed directly on the surface of the Si substrate. Because the boron silicide film is chemically and physically stable, an improved diffusion controllability is obtained. The diffusion controllability is further improved by accurately evaluating the impurity film optically during the fabrication process.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: May 19, 1998
    Assignee: Seiko Instruments, Inc.
    Inventors: Tadao Akamine, Naoto Saito, Kenji Aoki, Yoshikazu Kojima
  • Patent number: 5744850
    Abstract: A novel photoelectric conversion semiconductor device having an amplifying function which can be readily fabricated is provided. An N.sup.+ -type impurity domain whose impurity concentration is higher than that of an N.sup.- -type semiconductor substrate is formed on one surface thereof and a P.sup.+ -type impurity domain is formed on the opposite surface. An SiO.sub.2 film, an Si.sub.3 N.sub.4 film and an SiO.sub.2 film are formed extending to the domain of the N.sup.- -type semiconductor substrate, exceeding the N.sup.+ -type impurity domain. An anode electrode is formed on the N.sup.+ -type impurity domain and a cathode electrode is formed on the P.sup.+ -type impurity domain. A polysilicon gate electrode is formed on the SiO.sub.2 film, i.e. the top layer, and an Al gate electrode is formed thereon. A reverse voltage is applied between the anode electrode and the cathode electrode and a predetermined voltage is applied between the anode electrode and the Al gate electrode.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: April 28, 1998
    Assignee: Seiko Instruments R&D Center Inc.
    Inventors: Keiji Sato, Yutaka Saitoh, Tadao Akamine
  • Patent number: 5719414
    Abstract: A photoelectric conversion semiconductor device is characterized in that a second conductivity type impurity region is formed in a first conductivity type semiconductor substrate, the second conductivity type impurity region having a depth of 0.1 .mu.m or less and a peak density of 1.times.10.sup.19 atoms/cm.sup.3 or more. A method of manufacturing a photoelectric conversion semiconductor device is characterized by a step of ion-injecting boron or boron fluoride with a dose amount of 1.times.10.sup.16 to 5.times.10.sup.16 atoms/cm.sup.2 into a semiconductor substrate as an impurity.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: February 17, 1998
    Inventors: Keiji Sato, Yutaka Saito, Tadao Akamine, Junko Yamanaka
  • Patent number: 5532185
    Abstract: The surface of a silicon wafer is cleaned to expose chemically active surface. Diborane gas is fed to the exposed active surface for adsorbing boron to the active surface. The adsorbed boron on the silicon wafer works as an impurity diffusion source. Boron is diffused from the impurity diffusion source into the silicon wafer to make an impurity diffusion layer by heat treatment. The amount of diborane gas fed to the active surface is set in an amount at which the sheet resistance of the impurity diffusion layer does not depend on variations in feed amount.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: July 2, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Tadao Akamine, Naoto Saito, Kenji Aoki
  • Patent number: 5514620
    Abstract: A PN junction device is formed by removing an inert film from a surface of an N type semiconductor layer to expose an active face, then applying a source gas containing an P type impurity component to the active face to form an impurity adsorption film, and thereafter carrying out a solid-phase diffusion of the impurity is carried out from a diffusion source composed of the P type impurity adsorption film into the N type semiconductor layer to form therein a P type semiconductor layer to thereby provide a PN junction. Lastly, a pair of electrodes are connected to the respective semiconductor layers to form the an PN junction device.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: May 7, 1996
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Naoto Saito
  • Patent number: 5338697
    Abstract: An exposed active surface is prepared on a major surface of a semiconductor substrate. A source gas containing an impurity component is applied to the exposed active surface to adsorb thereon a film of the impurity component so as to form a barrier region along the major surface of the semiconductor substrate. A semiconductor device is formed on the major surface of the semiconductor substrate and is protected by the barrier region.
    Type: Grant
    Filed: December 3, 1990
    Date of Patent: August 16, 1994
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Naoto Saito
  • Patent number: 5124272
    Abstract: An impurity adsorption layer is selectively formed from a gas containing an impurity on a semiconductor surface. Solid-phase diffusion of the impurity is effected from the impurity adsorption layer into the semiconductor surface to form a source region and a drain region having a sufficiently small resistivity and an ultrashallow PN junction depth, thereby producing a metal-insulator semiconductor field-effect-transistor featuring fast operating speed and reduced dimensions.
    Type: Grant
    Filed: August 13, 1990
    Date of Patent: June 23, 1992
    Assignee: Seiko Instruments, Inc.
    Inventors: Naoto Saito, Kenji Aoki, Tadao Akamine, Yoshikazu Kojima, Kunihiro Takahashi, Masahiko Kinbara