Patents by Inventor Tadao Kanezuka

Tadao Kanezuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MIS logical circuit
    Patent number: 4016430
    Abstract: In a logical circuit comprising a load and a driving MISFET, a depletion type MISFET is connected between the load and the driving MISFET and a voltage which has a smaller absolute value than the absolute value of the difference between a supply voltage and a threshold voltage of the depletion type MISFET is impressed on the gate electrode of the depletion type MISFET.
    Type: Grant
    Filed: December 23, 1975
    Date of Patent: April 5, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Tadao Kanezuka