Abstract: In an integrated circuit comprising an IIL and a high frequency npn bipolar transistor which has a deep p.sup.- -type base region 45 for its inverted npn output transistors, circuit elements such as a resistor part R, a capacitor part C, a diode part D and an isolated crossing connection part Cr are provided with deep p.sup.- -type regions 54, 54', 65', 71 and 82 which are formed at the same time with the p.sup.- -type region 45 in the IIL, and thereby, reliability of the circuit elements as well as characteristic thereof are improved, thereby further improving manufacturing yields.

Abstract: Disclosed is a structure of a semiconductor integrated circuit such as bipolar transistor, along with the fabrication thereof, in which an active device region such an intrinsic base is formed from, at least, the bottom of the groove formed in a semiconductor substrate, and this active device region and a low resistance electrode take-out region such an extrinsic base formed around the groove are connected favorably with each other.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: A method for fabricating a semiconductor device which is capable of enlarging diameter of crystal grain of a polycrystalline conductor by a heat treatment which is carried out after surface lower portion of the polycrystalline conductor is made amorphous with ion-implanting atoms in the polycrystalline conductor by predetermined accelerating energy to thereby improve the uniformity of size of crystal grain. By this method, the uniformity of impurity concentration distribution is improved in the polycrystalline conductor and also in the impurity diffusion area, and further, the uniformity of resistance of a resistor or conductor formed by the polycrystalline conductor is improved.

Abstract: A semiconductor integrated circuit device includes first and second grooves extending in a silicon semiconductor substrate, a shallow groove extending between the first and second grooves and contiguous with the first and second grooves, and insulating material occupying the first and second deep grooves and said shallow groove. Accordingly, by forming grooves having two different depths, the deep groove can be filled without increasing the thickness of the insulating layer, and moreoever, an insulating isolation region having a flat upper surface can be obtained.

Abstract: In a method for fabricating a favorable bipolar semiconductor device in which the extrinsic base and emitter diffusion holes are formed in self-alignment, an optimum structure between the extrinsic base and instrinsic base is realized. By controlling the concentration of the impurities in the extrinsic base, the base contact and emitter region can be finely formed in self-alignment, and occurence of damage or contamination in the intrinsic base region is inhibited.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: A method of fabrication of a semiconductor device by forming a thin film pattern in the emitter region, forming a base lead-out electrode self-aligningly by using this thin film pattern, and also forming a fine graft base region and emitter region, and an oxide film for isolating the emitter region and base region, whereby the emitter diffusion layer and active base diffusion layer are formed in a shallow depth of diffusion by heat diffusion from the semiconductor film in which ions are implanted.

Abstract: A solid-state imaging device comprising a semiconductor circuit substrate having regions for storage and transfer of signal charges, an insulating film formed on the substrate and a photoconductive film. A light shielding member is provided in the insulating film on the semiconductor circuit substrate. An opening is formed in the insulating film in registry with the charge storage region and an electroconductive film is embedded in the opening. With this construction of the device, blooming is suppressed and the characteristics of the photoconductive film are improved.

Abstract: A method for manufacturing a semiconductor integrated circuit which comprises providing a semiconductor substrate, forming a recess in the substrate through a pattern of an oxidation-inhibiting film, forming a thin film of a material capable of being oxidizing into an insulating oxide such as silicon on the side and/or bottom surface of the recess, and oxidizing the thin film to fill up with the recess with the resulting oxide which increases in volume.

Abstract: In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

Abstract: An IC device comprising a junction type field effect transistor of a back gate type and a bipolar device such as a bipolar transistor and a resistor made of impurity diffused region, wherein an extremely thin (in the order of 0.05-0.2 .mu.m) impurity doped surface region of a conductivity type same as that of a back gate region is formed at the surface of a surface channel region, and is separated from at least a drain region to sustain high breakdown voltage between gate region and the drain region; the impurity surface region serving to reduce noise and also enabling to achieve satisfactory characteristics of J-FET and also good ohmic characteristics of the resistor.

Abstract: A process for fabrication of semiconductor devices comprising the steps of depositing over the surface of a semiconductor wafer a first insulating layer containing impurities which are to be diffused into the wafer so as to form source and drain regions, depositing a second insulating and melt-flow layer which is softened or melted at low temperatures, opening contact windows, forming a third insulating layer which also contains impurities to be diffused into the wafer so as to form source drain regions, subjecting the wafer to a heat treatment so as to cause melt-flow and form source and drain regions by the diffusion and removing the third insulating layer. LSI circuits with a high source-drain breakdown voltage may be fabricated at high yields.