Patents by Inventor Tadao Kushima
Tadao Kushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7141741Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.Type: GrantFiled: September 22, 2003Date of Patent: November 28, 2006Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Publication number: 20040056349Abstract: A semiconductor device in which electrodes of a plurality of semiconductor elements are bonded onto at least one of a plurality of electrode patterns on an insulator substrate, the other surface of the insulator substrate being bonded to a heat dissipating base. The upper surface of the heat dissipating base is covered with a member for cutting off the semiconductor elements from the outer environment. Terminals electrically connect the electrodes on said insulator substrate and the electrode placed outside the cutoff member. The material of the heat dissipating base has a linear expanding coefficient larger than that of the semiconductor element and smaller than three times that of the semiconductor element, and a thermal conductivity larger than 100 W/mK. The semiconductor elements are arranged on at least one electrode surface and in at least two regions divided by the other electrode surface on the insulator substrate.Type: ApplicationFiled: September 22, 2003Publication date: March 25, 2004Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Publication number: 20030016502Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: ApplicationFiled: March 20, 2002Publication date: January 23, 2003Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 6441317Abstract: In a semiconductor module comprising, a semiconductor element, an electrically insulating base having an outer surface to be connected to an electrically grounded surface, and an inner surface on which the semiconductor element is arranged, an electrically insulating cover covering the semiconductor element on the inner surface, and first and second electrically conductive members each of which is connected to the semiconductor element and extends to the exterior of the semiconductor module through the electrically insulating cover, a part of each of the first and second electrically conductive members on the exterior of the semiconductor module is arranged away from the outer surface to electrically isolate the part of the each of the first and second electrically conductive members from the electrically grounded surface.Type: GrantFiled: September 1, 2000Date of Patent: August 27, 2002Assignee: Hitachi, Ltd.Inventors: Akira Tanaka, Ryuichi Saito, Tadao Kushima, Yoshihiko Koike, Hideo Shimizu, Shigeharu Nonoyama
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Patent number: 6434008Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: GrantFiled: August 27, 1998Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 5956231Abstract: A semiconductor device in which a plurality of semiconductor elements are bonded onto at least one electrode pattern on an insulator substrate formed a plurality of electrode patterns on the main surface, each of the electrodes of the semiconductor element being electrically connected to the electrode pattern, the other surface of the insulator substrate being bonded to a heat dissipating base, the upper surface of the heat dissipating base being covered with a member for cutting off the semiconductor elements from the outer environment, terminals electrically connecting the electrodes on said insulator substrate and the electrode placed outside the cutoff member being provided, wherein the material of the heat dissipating base has a linear expanding coefficient larger than the linear expansion coefficient of the semiconductor element and smaller than three times of the linear expansion coefficient of the semiconductor element, and a thermal conductivity larger than 100 W/mK, the semiconductor elements beingType: GrantFiled: October 4, 1995Date of Patent: September 21, 1999Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuji Yamada, Akira Tanaka, Ryuichi Saito, Yasutoshi Kurihara, Tadao Kushima, Takashi Haramaki, Yoshihiko Koike, Takashi Hosokawa, Mamoru Sawahata, Masahiro Koizumi, Jin Onuki, Kazuhiro Suzuki, Isao Kobayashi, Hideo Shimizu, Yutaka Higashimura, Shigeki Sekine, Nobuya Koike, Hideya Kokubun
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Patent number: 4906823Abstract: The invention relates to a solder carrier comprising a sheet of self-support type, made of a material which does not react to a solder when it is melted, a plurality of small through holes, and solder filling the through holes, each of the small through holes having an end, the area of which is larger than that of the other end. By using this solder carrier, a semiconductor device can be flip-chip-connected to a carrier substrate through a bump method, and solder balls can be formed for connecting the carrier substrate to a multilayer circuit board. The through holes of the solder carrier, each of which holes is to be filled with solder, is formed by etching, and the solder is inserted in the holes under pressure by a roll or the like.Type: GrantFiled: June 3, 1988Date of Patent: March 6, 1990Assignee: Hitachi, Ltd.Inventors: Tadao Kushima, Tasao Soga, Kazuji Yamada, Mitugu Shirai
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Patent number: 4825284Abstract: A semiconductor resin package structure formed according to the flip-chip connection method and permitting to cool the rear surface of semiconductor chips, comprising semiconductor chip and carrier substrate which is soldered on one surface thereof to electrodes of the semiconductor chip according to the flip-chip connection method, the gap between the semiconductor chip and the carrier substrate being filled with resin having a thermal expansion coefficient, which is approximately equal to that of used solder, the electrodes of the semiconductor chip being electrically connected with terminals on the other surface of the carrier substrate through the soldered portions and a through-hole conductor disposed on the carrier substrate, the thermal expansion coefficient of the carrier substrate being approximately equal to that of a multi-layer substrate, with which the substrate is connected by soldering with the terminals.Type: GrantFiled: December 10, 1986Date of Patent: April 25, 1989Assignee: Hitachi, Ltd.Inventors: Tasao Soga, Marahiro Goda, Fumio Nakano, Tadao Kushima, Nobuyuki Ushifusa, Fumiyuki Kobayashi, Mamoru Sawahata
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Patent number: 4562637Abstract: A method of manufacturing a solar battery by serially connecting a plurality of solar battery elements arranged spaced from each other. A pair of flexible films are used to sandwich the arrangement of the solar battery elements, and each of the flexible films has a plurality of conductive members formed thereon at positions respectively corresponding to the solar battery elements. However, each conductive member has one end portion extended beyond the surface of the corresponding solar battery element in the direction of the alignment of the solar battery elements. Thus, when the pair of flexible films are disposed to sandwich the solar battery elements, the extended end portion of the conductive member on the side of the light receiving surface of one solar battery element is positioned in the space between adjacent solar battery elements opposite the end portion of the conductive member on the side of the back surface of the next solar battery element.Type: GrantFiled: June 20, 1984Date of Patent: January 7, 1986Assignee: Hitachi, Ltd.Inventors: Tadao Kushima, Tasao Soga, Takaya Suzuki
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Patent number: 4503597Abstract: A method of forming a number of discrete solder layers on a semiconductor wafer of a large area. A number of regions which are easy to be wetted with solder are formed on one of the major surfaces of the wafer. A solder foil is positioned on the one major surface and a plate-like jig including a plate and projections formed on one surface thereof is disposed on the solder foil with the projections facing the latter. By heating the stacked assembly at a sufficiently high temperature for the solder foil to be molten, a number of the discrete solder layers having a uniform thickness are formed on the semiconductor wafer.Type: GrantFiled: February 7, 1983Date of Patent: March 12, 1985Assignee: Hitachi, Ltd.Inventors: Tadao Kushima, Masahiro Gooda, Tasao Soga, Toshitaka Yamamoto