Patents by Inventor Tadao MORIMOTO

Tadao MORIMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825166
    Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 21, 2017
    Assignee: HITACHI, LTD.
    Inventors: Naoki Tega, Digh Hisamoto, Satoru Akiyama, Takashi Takahama, Tadao Morimoto, Ryuta Tsuchiya
  • Publication number: 20150349115
    Abstract: Disclosed herein is a technique for realizing a high-performance and high-reliability silicon carbide semiconductor device. A trenched MISFET with a trench formed into the drift through a p-type body layer 105 includes an n-type resistance relaxation layer 109 covering the bottom portion of the trench, and a p-type field relaxation layer 108. The p-type field relaxation layer 108 is separated from the trench bottom portion via the resistance relaxation layer 109, and is wider than the resistance relaxation layer 109. This achieves a low ON resistance, high reliability, and high voltage resistance at the same time. By forming the field relaxation layer beneath the trench, feedback capacitance can be controlled to achieve a high switching rate and high reliability.
    Type: Application
    Filed: January 23, 2013
    Publication date: December 3, 2015
    Inventors: Naoki TEGA, Digh HISAMOTO, Satoru AKIYAMA, Takashi TAKAHAMA, Tadao MORIMOTO, Ryuta TSUCHIYA