Patents by Inventor Tadao Tanikawa
Tadao Tanikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9460276Abstract: A virtual machine system that restricts use of confidential information only to the case where an authentication has resulted in success. The virtual machine system includes first virtual machine, second virtual machine, and hypervisor. The first virtual machine includes: storage unit storing confidential information; and authentication unit configured to perform authentication and notify the hypervisor of result of the authentication. The second virtual machine uses virtual device that is virtualized storage device. When having received authentication result indicating authentication success from the authentication unit, the hypervisor enables the second virtual machine to access, as substance of the virtual device, storage area storing the confidential information, and when not having received the authentication result indicating the authentication success from the authentication unit, the hypervisor disables the second virtual machine from accessing the storage area storing the confidential information.Type: GrantFiled: February 20, 2013Date of Patent: October 4, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Tadao Tanikawa, Masahiko Saito, Katsushige Amano, Toshiaki Takeuchi
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Patent number: 9170832Abstract: A virtual machine control apparatus 100 controls execution of a first type virtual machine A210 and a second type virtual machine 220. The first type virtual machine A210 includes a start detection unit 261 which detects an operation in the first type virtual machine A210 to start usage of a device (external storage device 160). The first type virtual machine A210 also includes a start signal output unit 262 which outputs a start signal when the start detection unit 261 detects the operation to start usage of the device. The second type virtual machine 220 includes a control unit (external storage device driver 272) which, when the start signal output unit 262 outputs the start signal while the device is in set in a low power mode (electrical power set to off), sets the device in a normal mode (electrical power set to on).Type: GrantFiled: January 25, 2013Date of Patent: October 27, 2015Assignee: Panasonic Intellectual Property Corporation of AmericaInventors: Katsushige Amano, Masahiko Saito, Tadao Tanikawa, Takuya Kondoh, Toshiaki Takeuchi
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Patent number: 9069589Abstract: The present invention relates to a virtual machine system that includes a plurality of processors and executes a plurality of virtual machines in parallel with use of the plurality of processors. An aim thereof is to suppress power consumption without sacrificing the performance of the virtual machine system. When there are at least two processors that do not have any virtual machines allocated thereto, one of the at least two processors is supplied with power so as to be placed in a standby state, and a remaining one or more of the at least two processors are not supplied with power.Type: GrantFiled: June 27, 2011Date of Patent: June 30, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Masahiko Saito, Ryota Miyazaki, Tadao Tanikawa, Katsushige Amano, Masashi Sugiyama
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Patent number: 9032401Abstract: When a process judging unit judges that a target process is a protected process, a key judging unit judges whether a target key that is a key generated by a key generating unit is a first key or a second key. When the key judging unit judges that the target key is the first key, a VM communication managing unit notifies the target process of a memory ID of a protected memory region corresponding to the first key. When the process judging unit judges that the target process is an unprotected process, a key transforming unit transforms the target key from the first key to the second key based on the key transformation rule. An HV communication managing unit notifies the target process of a memory ID of an unprotected memory region corresponding to the second key.Type: GrantFiled: March 30, 2012Date of Patent: May 12, 2015Assignee: Panasonic Intellectual Property Corporation of AmericaInventors: Teruo Kamiyama, Katsushige Amano, Masahiko Saito, Tadao Tanikawa
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Patent number: 8819680Abstract: A computer system enables two virtual machines with use of two virtual CPUs. The computer system includes a CPU that is allocated to the virtual CPU when the virtual CPU performs computer processing of the virtual machine other than timer processing; a tick CPU that is dedicated to timer processing and is allocated to the virtual CPU upon receiving an interrupt request (tick interrupt) for causing the virtual CPU to perform timer processing of the virtual machine; and interrupt controller that issues the tick interrupt to the tick CPU.Type: GrantFiled: June 9, 2011Date of Patent: August 26, 2014Assignee: Panasonic Intellectual Property Corporation of AmericaInventors: Tadao Tanikawa, Katsushige Amano
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Publication number: 20140196034Abstract: A virtual machine control apparatus 100 controls execution of a first type virtual machine A210 and a second type virtual machine 220. The first type virtual machine A210 includes a start detection unit 261 which detects an operation in the first type virtual machine A210 to start usage of a device (external storage device 160). The first type virtual machine A210 also includes a start signal output unit 262 which outputs a start signal when the start detection unit 261 detects the operation to start usage of the device. The second type virtual machine 220 includes a control unit (external storage device driver 272) which, when the start signal output unit 262 outputs the start signal while the device is in set in a low power mode (electrical power set to off), sets the device in a normal mode (electrical power set to on).Type: ApplicationFiled: January 25, 2013Publication date: July 10, 2014Applicant: PANASONIC CORPORATIONInventors: Katsushige Amano, Masahiko Saito, Tadao Tanikawa, Takuya Kondoh, Toshiaki Takeuchi
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Patent number: 8726056Abstract: An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.Type: GrantFiled: January 9, 2012Date of Patent: May 13, 2014Assignee: Panasonic CorporationInventors: Ryo Yokoyama, Tadao Tanikawa
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Publication number: 20140020086Abstract: A virtual machine system that restricts use of confidential information only to the case where an authentication has resulted in success. The virtual machine system includes first virtual machine, second virtual machine, and hypervisor. The first virtual machine includes: storage unit storing confidential information; and authentication unit configured to perform authentication and notify the hypervisor of result of the authentication. The second virtual machine uses virtual device that is virtualized storage device. When having received authentication result indicating authentication success from the authentication unit, the hypervisor enables the second virtual machine to access, as substance of the virtual device, storage area storing the confidential information, and when not having received the authentication result indicating the authentication success from the authentication unit, the hypervisor disables the second virtual machine from accessing the storage area storing the confidential information.Type: ApplicationFiled: February 20, 2013Publication date: January 16, 2014Applicant: Panasonic CorporationInventors: Tadao Tanikawa, Masahiko Saito, Katsushige Amano, Toshiaki Takeuchi
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Patent number: 8544011Abstract: A job control information storing section stores execution conditions under which execution of tasks is started, and an execution order of the tasks. A job executing section executes the tasks. A job execution administering section monitors a state of the task being executed to detect the task whose state is shifted to a process standby state of waiting for a response from another one of the tasks, based on the execution conditions, and responds to a request of executing the another task from the task whose state is shifted, in response to accepting the request from the task whose state is shifted. A virtual task generating section generates a virtual task as a copy of the task whose state is detected to be shifted. A virtual task registering section adds the virtual task to the execution order to concurrently execute the virtual task with the task whose state is shifted.Type: GrantFiled: June 25, 2009Date of Patent: September 24, 2013Assignee: Panasonic CorporationInventor: Tadao Tanikawa
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Patent number: 8504752Abstract: The interrupt level storing unit (16) stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit (13) sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit (14) notifies the interrupt to the virtual machine control unit (20) when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.Type: GrantFiled: June 23, 2009Date of Patent: August 6, 2013Assignee: Panasonic CorporationInventors: Katsuhiro Arinobu, Tadao Tanikawa, Katsushige Amano
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Publication number: 20130117745Abstract: When a process judging unit 109 judges that a target process is a protected process 101, a key judging unit 111 judges whether a target key that is a key generated by a key generating unit 108 is a first key or a second key. When the key judging unit 111 judges that the target key is the first key, a VM communication managing unit 112 notifies the target process of a memory ID of a protected memory region 121 corresponding to the first key. When the process judging unit 109 judges that the target process is an unprotected process, a key transforming unit 110 transforms the target key from the first key to the second key based on the key transformation rule. An HV communication managing unit 105 notifies the target process of a memory ID of an unprotected memory region 122 corresponding to the second key.Type: ApplicationFiled: March 30, 2012Publication date: May 9, 2013Inventors: Teruo Kamiyama, Katsushige Amano, Masahiko Saito, Tadao Tanikawa
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Publication number: 20130081016Abstract: The present invention relates to a virtual machine system that includes a plurality of processors and executes a plurality of virtual machines in parallel with use of the plurality of processors. An aim thereof is to suppress power consumption without sacrificing the performance of the virtual machine system. When there are at least two processors that do not have any virtual machines allocated thereto, one of the at least two processors is supplied with power so as to be placed in a standby state, and a remaining one or more of the at least two processors are not supplied with power.Type: ApplicationFiled: June 27, 2011Publication date: March 28, 2013Inventors: Masahiko Saito, Ryota Miyazaki, Tadao Tanikawa, Katsushige Amano, Masashi Sugiyama
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Patent number: 8374842Abstract: An access monitoring section (11) obtains access information including an address conforming to an address stored in a monitoring address setting section (10) from an access signal output from a CPU (1) to a peripheral device (3). An access judging section (13) compares the access information received from the access monitoring section (11) and the last access information stored in an access storing section (12), and stores the obtained access information in the access storing section (12) and requests the transmission of an exception generation notification to an exception generating section (14) when the received access information is different from the last access information while excluding the last access information stored in the access storing section (12) from access information to be compared when the received access information is the same as the last access information. By this construction, throughput can be reduced at the time of emulation and the peripheral device can be efficiently emulated.Type: GrantFiled: May 20, 2009Date of Patent: February 12, 2013Assignee: Panasonic CorporationInventors: Katsushige Amano, Tadao Tanikawa
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Publication number: 20120331465Abstract: A memory protection unit controls access by virtual machines to memory areas. By having a hypervisor executed by a processor and the memory protection unit cooperate, access to memory areas by each virtual machine is controlled such that access to designated areas is forbidden. Accordingly, each virtual machine is unable to access programs, data, and so on stored in areas forbidden thereto.Type: ApplicationFiled: September 12, 2011Publication date: December 27, 2012Inventor: Tadao Tanikawa
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Publication number: 20120174098Abstract: A computer system enables two virtual machines 110 and 111 with use of two virtual CPUs 143 and 144. The computer system includes: CPU 103 that is allocated to the virtual CPU 143 when the virtual CPU 143 performs computer processing of the virtual machine 110 other than timer processing; tick CPU 105 that is dedicated to timer processing and is allocated to the virtual CPU 143 upon receiving an interrupt request (tick interrupt) for causing the virtual CPU 103 to perform timer processing of the virtual machine 110; and interrupt controller 106 that issues the tick interrupt to the tick CPU 105.Type: ApplicationFiled: June 9, 2011Publication date: July 5, 2012Inventors: Tadao Tanikawa, Katsushige Amano
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Publication number: 20120110366Abstract: An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.Type: ApplicationFiled: January 9, 2012Publication date: May 3, 2012Inventors: Ryo YOKOYAMA, Tadao TANIKAWA
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Patent number: 8117474Abstract: An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.Type: GrantFiled: December 10, 2008Date of Patent: February 14, 2012Assignee: Panasonic CorporationInventors: Ryo Yokoyama, Tadao Tanikawa
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VIRTUAL MACHINE CONTROL DEVICE, VIRTUAL MACHINE CONTROL PROGRAM, AND VIRTUAL MACHINE CONTROL CIRCUIT
Publication number: 20110106993Abstract: The interrupt level storing unit (16) stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit (13) sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit (14) notifies the interrupt to the virtual machine control unit (20) when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.Type: ApplicationFiled: June 23, 2009Publication date: May 5, 2011Inventors: Katsuhiro Arinobu, Tadao Tanikawa, Katsushige Amano -
Publication number: 20100325469Abstract: An instruction detecting section (235) detects whether or not there is any succeeding instruction executable regardless of an order based on a data dependency relationship between a presently executed instruction and a succeeding instruction following the presently executed instruction. A clock switch judging section (236) receives notification of the start and end of a memory stall, determines whether or not a memory stall is occurring, and judges whether to switch a clock signal to be supplied to a CPU (200) to a low clock signal (239) or to stop the clock signal based on a detection result of the instruction detecting section (235) if it is judged that the memory stall is occurring. A clock switching section (237) switches the clock signal based on judgment by the clock switch judging section (236). By this construction, power consumption can be reduced without reducing performance.Type: ApplicationFiled: December 10, 2008Publication date: December 23, 2010Inventors: Ryo Yokoyama, Tadao Tanikawa
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Publication number: 20100231959Abstract: A job control information storing section (111) stores execution conditions under which execution of the respective tasks is started, and an execution order of the tasks. A job executing section (101) executes the tasks in accordance with the execution order. A job execution administering section (102) monitors a state of the task being executed to detect the task whose state is shifted to a process standby state of waiting for a response from another one of the tasks, based on the execution conditions, and responds to a request of executing the another task from the task whose state is shifted to the process standby state, in response to accepting the request from the task whose state is shifted to the process standby state. A virtual task generating section (121) generates a virtual task as a copy of the task whose state is detected to be shifted to the process standby state.Type: ApplicationFiled: June 25, 2009Publication date: September 16, 2010Inventor: Tadao Tanikawa