Patents by Inventor Tadashi Atoji
Tadashi Atoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8029685Abstract: A method of manufacturing a liquid ejection head and a liquid ejection head capable of preventing corrosion of electrodes are provided. The method of manufacturing a liquid ejection head includes: a step of forming porous silicon areas in portions of a silicon substrate where the liquid paths are to be formed; a step of forming in layers in the porous silicon areas a protective layer, a heating resistor layer, an electrode layer and a heat accumulation layer; a step of forming ink ejection openings in the silicon substrate; and a step of removing the porous silicon areas.Type: GrantFiled: September 4, 2007Date of Patent: October 4, 2011Assignee: Canon Kabushiki KaishaInventors: Hirokazu Komuro, Makoto Kurotobi, Tadashi Atoji, Takehito Okabe
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Patent number: 7642112Abstract: A method of manufacturing a bonded substrate stack includes a bonding surface processing step of processing at least one of first and second substrates each containing silicon and having a bonding surface, and a bonding step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate. The bonding surface processing step includes an OH group increasing step of increasing OH groups on the bonding surfaces, and a moisture content decreasing step of heating the bonding surfaces where the OH groups have been increased at a temperature falling within a range of 50° C. to 200° C. to decrease moisture contents of the bonding surfaces.Type: GrantFiled: September 9, 2005Date of Patent: January 5, 2010Assignee: Canon Kabushiki KaishaInventors: Tadashi Atoji, Ryuji Moriwaki
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Publication number: 20080076197Abstract: A method of manufacturing a liquid ejection head and a liquid ejection head capable of preventing corrosion of electrodes are provided. A method of manufacturing a liquid ejection head includes: a steps of forming porous silicon areas in portions of a silicon substrate where the liquid paths are to be formed; a steps of forming in layers in the porous silicon areas a protective layer, a heating resistor layer, an electrode layer and a heat accumulation layer; a steps of forming ink ejection openings in the silicon substrate; and a steps of removing the porous silicon areas.Type: ApplicationFiled: September 4, 2007Publication date: March 27, 2008Applicant: CANON KABUSHIKI KAISHAInventors: Hirokazu Komuro, Makoto Kurotobi, Tadashi Atoji, Takehito Okabe
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Publication number: 20070243330Abstract: Disclosed is a manufacturing method of a liquid discharge head having a discharge port which discharges a liquid, a flow path which communicates with the discharge port, a heating portion which is disposed correspondingly to the flow path and which generates heat energy for use in discharging the liquid from the discharge port and a protective layer which prevents the heating portion from being brought into contact with the liquid, the method comprising: forming porous silicon from a surface to an inner portion of a silicon substrate; sealing pores present in the surface of the porous silicon to smoothen the surface of the porous silicon; forming the protective layer on the smoothened surface of the porous silicon; forming the heating portion on the protective layer; forming the discharge port; and removing the porous silicon to form the flow path.Type: ApplicationFiled: March 29, 2007Publication date: October 18, 2007Applicant: CANON KABUSHIKI KAISHAInventors: Hirokazu Komuro, Makoto Kurotobi, Tadashi Atoji, Takehito Okabe
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Patent number: 7245002Abstract: A semiconductor substrate which effectively prevents a chipping phenomenon, wherein the outer peripheral extremity of the insulation layer is located between the outer peripheral extremity of the semiconductor layer and the outer peripheral extremity of the support member, and wherein the semiconductor layer and the insulation layer produce a stepped profile.Type: GrantFiled: May 13, 2002Date of Patent: July 17, 2007Assignee: Canon Kabushiki KaishaInventors: Yutaka Akino, Tadashi Atoji
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Publication number: 20070114609Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.Type: ApplicationFiled: January 22, 2007Publication date: May 24, 2007Inventors: YUTAKA AKINO, Tadashi Atoji
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Publication number: 20060073644Abstract: A method of manufacturing a bonded substrate stack includes a bonding surface processing step of processing at least one of first and second substrates each containing silicon and having a bonding surface, and a bonding step of bonding the bonding surface of the first substrate and the bonding surface of the second substrate. The bonding surface processing step includes an OH group increasing step of increasing OH groups on the bonding surfaces, and a moisture content decreasing step of heating the bonding surfaces where the OH groups have been increased at a temperature falling within a range of 50° C. to 200° C. to decrease moisture contents of the bonding surfaces.Type: ApplicationFiled: September 9, 2005Publication date: April 6, 2006Inventors: Tadashi Atoji, Ryuji Moriwaki
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Publication number: 20020132451Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.Type: ApplicationFiled: May 13, 2002Publication date: September 19, 2002Inventors: Yutaka Akino, Tadashi Atoji
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Patent number: 6417108Abstract: A method of manufacturing a semiconductor substrate can effectively prevent a chipping phenomenon and the production of debris from occurring in part of the insulation layer and the semiconductor by removing a outer peripheral portion of the semiconductor substrate so as to make the outer peripheral extremity of the insulation layer to be located between the outer peripheral extremity of the semiconductor layer and that of the support member and hence the semiconductor layer and the insulation layer produce a stepped profile.Type: GrantFiled: January 28, 1999Date of Patent: July 9, 2002Assignee: Canon Kabushiki KaishaInventors: Yutaka Akino, Tadashi Atoji
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Publication number: 20020004286Abstract: A method of manufacturing a high-quality bonded SOI substrate is provided. The step of exposing the bonding interface between two substrates is performed in an atmosphere having cleanliness of Class 1 or more in Fed. St. 209D: USA IS standard. A clean room of Class 1 can be obtained using an air filter having a collection efficiency of 99.9999% (6N) or more for dust particles of a size of 0.1 &mgr;m or more.Type: ApplicationFiled: March 1, 1999Publication date: January 10, 2002Applicant: Canon Kabushiki KaishaInventor: TADASHI ATOJI
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Patent number: 6156624Abstract: This invention solves the problem of a pasted SOI substrate generating voids in the peripheral part thereof and consequently decreasing the number of devices to be derived therefrom. It concerns a method for the production of a SOI substrate obtained by pasting a first Si substrate possessing a SiO.sub.2 surface and a second substrate possessing a Si surface on the SiO.sub.2 surface and the Si surface, which method comprises washing the Si surface of the second Si substrate, thereby imparting hydrophobicity to the Si surface before the first Si substrate and the second Si substrate are pasted together.Type: GrantFiled: April 4, 1997Date of Patent: December 5, 2000Assignee: Canon Kabushiki KaishaInventors: Kenji Yamagata, Takao Yonehara, Tadashi Atoji, Kiyofumi Sakaguchi
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Patent number: 6103009Abstract: A process for fabricating a SOI substrate efficiently removes a non-porous Si region on a porous Si region, and solves the problem of etching of glass substrates and the problem that a relatively thick porous Si region is necessary.Type: GrantFiled: December 9, 1996Date of Patent: August 15, 2000Assignee: Canon Kabushiki KaishaInventor: Tadashi Atoji
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Patent number: 6054363Abstract: A method of manufacturing a semiconductor article comprises steps of preparing a first substrate including a silicon substrate having a porous silicon layer and a nonporous semiconductor layer arranged on the porous silicon layer, bonding the first substrate and a second substrate to produce a multilayer structure with the nonporous semiconductor layer located inside, separating the first and second substrates of the multilayer structure from each other along the porous silicon layer by heating the multilayer structure and removing the porous silicon layer remaining on the separated second substrate.Type: GrantFiled: November 12, 1997Date of Patent: April 25, 2000Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Tadashi Atoji
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Patent number: 5876497Abstract: The conventional fabrication processes of SOI substrate employed wet etching for removing a porous single-crystal Si region, but wet etching involved difficulties in management of concentration for fabricating SOI substrates in high volume, which caused reduction in productivity.Therefore, provided is a fabrication process of SOI substrate comprises a step of forming a non-porous single-crystal Si region on a surface of a porous single-crystal Si region of a single-crystal Si substrate having at least the porous single-crystal Si region, a step of bonding a support substrate through an insulating region to a surface of the non-porous single-crystal Si region, and a step of removing the porous single-crystal Si region, wherein the step of removing the porous single-crystal Si region comprises a step of performing dry etching in which an etch rate of the porous single-crystal Si region is greater than that of the non-porous single-crystal Si region.Type: GrantFiled: December 9, 1996Date of Patent: March 2, 1999Assignee: Canon Kabushiki KaishaInventor: Tadashi Atoji
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Patent number: 5686734Abstract: A high performance thin film semiconductor device having a heterojunction such as a photoelectric conversion device is disclosed. In accordance with the present invention, the thin film semiconductor device comprises a thin semiconductor layer which forms a heterojunction with a non-single crystal silicon layer or non-single crystal silicon-germanium layer, wherein the valence band discontinuity at the heterointerface arising from the difference in optical energy bandgap is as small as 0.3 eV or less and wherein the thin semiconductor layer has an optical energy bandgap greater than 2.8 eV, so that hole transport performance may not be degraded. Such a thin semiconductor layer may be formed by using silane gas and methane gas with a flow rate ratio greater than 30 at a deposition rate less than 0.5 .ANG./sec.Type: GrantFiled: July 14, 1995Date of Patent: November 11, 1997Assignee: Canon Kabushiki KaishaInventors: Yoshihiro Hamakawa, Shigetoshi Sugawa, Tadashi Atoji, Hiroaki Okamoto
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Patent number: 5445992Abstract: A semiconductor film having a very high light response of photoconductivity and good electrical characteristics such a wide band gap, for example, a non-monocrystalline silicon carbide film, is formed by decomposition reaction of a silicon-containing raw material gas and a hydrocarbon as a carbon raw material under light irradiation or high frequency, where the carbon raw material gas comprises at least one of tertiary and quaternary carbon atom-containing hydrocarbons of specific chemical formulae, and a semiconductor device using the thus formed semiconductor film is also provided.Type: GrantFiled: May 5, 1994Date of Patent: August 29, 1995Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Tadashi Atoji