Abstract: The error rate of a signal is monitored by sampling an input signal with a first clock and also with second and third clocks phase delayed in equal but opposite directions with respect to the first clock, and then logically combining the first through third sampled outputs in order to obtain an error signal.

Abstract: A counter consists of, to simplify the control of component parts and to improve the productivity, a first frame unit comprising a plurality of digit wheels, a driving gear for a digit wheel of a lower most order, an order shifting-up means and a zero-resetting means, a second frame unit being capable to be snap fitted on the first frame unit and comprising a driving means to be coupled with the driving gear when attached to the first frame unit, and a cover frame unit being capable to be snap fitted on the first frame unit and to show only one line of the laterally lined digits when attached to cover the first frame unit. The second frame unit may be the base plate of the devices on which the counter will be used. The first frame unit may comprise only a plurality of digit wheels, a driving gear for a digit wheel of a lower most order and a zero-resetting button, and the second frame unit may comprise an order shifting-up means and a zero-resetting means.

Abstract: In a PSK carrier regenerating circuit, a second regeneration path is provided for regenerating a carrier which is less susceptible to cycle slip phase errors. A variable phase shifter is provided at the output of the first carrier regeneration path to selectively shift the phase thereof in accordance with a phase comparison of the first and second regenerated carriers.