Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

Abstract: A semiconductor device includes an inductor configured to supply a current to a first node based on a higher voltage region power supply voltage. A first switch is configured to selectively supply a current from the first node into a third node based on a voltage on a second node; a second switch is configured to selectively supply a current from the first node into the second node based on a voltage of the third node; a third switch is configured to supply the current from the third node into a ground terminal based on a lower voltage region input logic level; and a fourth switch is configured to be turned ON/OFF alternately with the third switch to supply the current from the second node to the ground terminal.

Abstract: A semiconductor circuit according to an embodiment of the invention includes: a terminal resistor circuit including a first Pch transistor; and a control circuit for outputting a control signal to a gate terminal of the first Pch transistor to control a resistance value of the terminal resistor circuit, the control circuit including: a second Pch transistor having a resistance value that is changed in the same direction as a resistance value of the second first transistor with respect to a specific parameter; and a resistor having a resistance value that is less changed than the resistance value of the second transistor with respect to the specific parameter, wherein the control circuit outputting the control signal based on a voltage between the second Pch transistor and the resistor.

Abstract: A semiconductor circuit according to an embodiment of the invention includes: a terminal resistor circuit including a first Pch transistor; and a control circuit for outputting a control signal to a gate terminal of the first Pch transistor to control a resistance value of the terminal resistor circuit, the control circuit including: a second Pch transistor having a resistance value that is changed in the same direction as a resistance value of the second first transistor with respect to a specific parameter; and a resistor having a resistance value that is less changed than the resistance value of the second transistor with respect to the specific parameter, wherein the control circuit outputting the control signal based on a voltage between the second Pch transistor and the resistor.

Abstract: An output buffer circuit includes a delay circuit for delaying data signal or an inverted version of the data signal by a preset time, a buffer for buffering the data signal with an output impedance of a high value to output the resulting buffered signal, and a three-state buffer, which is controlled responsive to the output of the delay circuit and to the data signal, so that the three-state buffer is activated within the preset time to buffer the data signal and to output the buffered data signal, and is de-activated and turned off outside the preset time.

Abstract: An infrared-rejecting device is positioned in a light path and tilted thereto to reflect infrared radiation and to prevent infrared radiation from being applied to a photodetector or a line sensor for preventing the photodetector or the line sensor from operating in error or from suffering a reduction in its resolution. The infrared-rejecting device may be positioned out of the light path to allow light applied to the photodetector or the line sensor to remain unattenuated, i.e., to prevent the light applied to the photodetector or the line sensor from being reduced in intensity.