Abstract: A microprocessor for processing a large quantity of graphics data. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. A graphics processing apparatus provided by the microprocessor transfers the graphics data between a system memory and a frame memory at high speeds.

Abstract: Heat radiating fin plates in a curved shape are radially arranged on a heat radiating surface of a heat transfer plate, and a space is provided so as to be surrounded by inner edges of the heat radiating fin plates. The heat radiating fin plates have sidewalls formed with projections.

Abstract: In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them.

Abstract: In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address so as to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them.

Abstract: In a graphic processing system, there are provided a main memory, a buffer containing a bit map memory for holding display data, a central processing unit for performing a data process involving a translation from a virtual address into a physical address to access the main memory, a graphic processor connected to the main memory and buffer, for processing data into a display form, and a system bus interface connected to the central processing unit, main memory and graphic processor, capable of exchanging the data among them.

Abstract: Apparatus for a multi-screen display including a multiprocessor for processing signals from at least one signal source and for applying processed signals to a plurality of display units arranged in at least two rows so as to form the multi-screen display. The multiprocessor includes vertical scanning format transformation apparatus for transforming a vertical scanning frequency of the output signal of the multiprocessor to be a higher vertical scanning frequency than that of a vertical scanning frequency of the input signal of the multiprocessor so that a ratio of the vertical scanning frequency of the output signal applied to the multi-screen display to the vertical scanning frequency of the input signal is at least two, thereby substantially eliminating discontinuity distortion of a moving pole image displayed as a reproduced picture on the multi-screen display.

Abstract: An LSI parallel image processor in which line buffers and data-flow switching circuits each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers is output from an image data output port, shift registers each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers are sequentially read out.

Abstract: A cursor display control in a graphic display system is provided in which a storage range is provided for exclusive use for a cursor pattern and a desired shape is defined in the storage range to thereby perform a high-speed cursor movement. A display control apparatus in the graphic display system includes a memory for storing a cursor pattern, shift register for performing a shift processing in a non-display period of the cursor for positioning in the display screen, and parallel-serial converter for performing parallel to serial conversion at the display timing of the cursor, whereby the apparatus is suitable to be integrated in the form of an LSI and the cursor can be moved at a high speed on the screen.

Abstract: A method of rendering an existing pipeline flexible, by cutting out an intermediate portion of a pipe in a ring form, inserting a pipe joint into a cutout position, and connecting the pipe joint to the pipe. The pipe joint used in this method includes a plurality of sleeves interconnected in a fluid-tight condition to be oscillatable relative to one another. The pipe joint is inserted into the cut-out position and connected to the pipe, with the plurality of sleeves substantially fixed to one another while being interconnected in the fluid-tight condition to be oscillatable relative to one another. The sleeves are thereafter released from the fixed state.

Abstract: A method of rendering an existing pipeline flexible, by cutting out an intermediate portion of a pipe in a ring form, inserting a pipe joint into a cutout position, and connecting the pipe joint to the pipe. The pipe joint used in this method includes a plurality of sleeves interconnected in a fluid-tight condition to be oscillatable relative to one another. The pipe joint is inserted into the cut-out position and connected to the pipe, with the plurality of sleeves substantially fixed to one another while being interconnected in the fluid-tight condition to be oscillatable relative to one another. The sleeves are thereafter released from the fixed state.

Abstract: A conversational picture processing system having a temporary memory for storing picture processing commands inputted by an operator. The system executes picture processing commands inputted by the operator, displays processed picture as a result of execution of each command, and stores the commands in the temporary memory. The system reads out a picture processing command specified by the operator from the temporary memory and stores the command as a registered command in a command list memory within the system.

Abstract: A multifunctional image processor capable of executing a variety of image processing functions such as a spatial convolution and a color image processing at a higher speed includes an image data distribute unit for distributing the gray-scale and color image data externally supplied by use of programs in accordance with the operation of the image processing and a parallel image data processing unit for conducting a parallel operation on distributed image data in accordance with the operation of the image processing.

Abstract: A high speed, multi-function and expandable image processing LSI (image signal processor) for realizing a gray level image processing technique is disclosed. The architecture of the image signal processor can process a gray level image having 256 tones at a video rate (256.times.256 image, 6 MHz, non-interlace), allows expansion of a partial operation area (kernel) and can carry out various partial neighborhood operations. The image signal processor is a partial parallel type image processing LSI which carries out a parallel operation by using the same number of processor elements as that of input pixel data used to produce one output pixel of data.

Abstract: An apparatus for parallelly processing image data from a local image data source, in which m rows x n columns of image data are processed by simultaneously processing n image data for each of the m rows (m and n being integers). The apparatus includes a member for serially receiving image data, a memory section having processing parameter data stored therein, a plurality of juxtaposed processor stages coupled to the memory section and arranged to be simultaneously supplied with sequentially shifted image data to thereby simultaneously produce processing results from the supplied image data and the processing parameter data, and an output section for receiving the outputs of the processor stages and delivering a processed output. The processing apparatus is suitable to be implemented in an IC form.