Abstract: A semiconductor device includes a variable resistor that sets a resistance value as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode, a first driver that sets an output impedance as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode, a second driver that sets the output impedance as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode, and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode.

Abstract: An apparatus for determining the density unevenness of an ink jet head includes a characteristic data generation unit which calculates characteristic values about ink amounts ejected from all nozzles of the ink jet head, respectively. A decision parameter acquisition unit arranges the characteristic values in the order the nozzles are arranged and calculates a decision parameter from changes in the characteristic values about those of the nozzles, which exist in a predetermined section. A decision unit compares the decision parameter with a predetermined threshold value, thereby determining the density unevenness of the ink jet head.

Abstract: A semiconductor device includes a variable resistor that sets a resistance value as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode, a first driver that sets an output impedance as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode, a second driver that sets the output impedance as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode, and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode.

Abstract: An image forming apparatus calculates an ink temperature considering a thermal capacity near nozzles and an ink circulation flow quantity of a circulation pump in addition to an ink temperature when flowing into a recording head and an ink temperature when flowing out of the recording head, and accurately estimates a waste amount of the ink ejected from the nozzles in, e.g., maintenance processing other than image formation.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: An ink-jet image recording apparatus is configured so that a sufficient hydraulic head difference can be secured to prevent ink overflow, and a pump on an ink feeding path leading to a recording head is driven to feed an ink toward the head, thereby pressuring overloaded nozzles to set a pressure for the formation of suitable menisci.

Abstract: An apparatus for determining the density unevenness of an ink jet head includes a characteristic data generation unit calculates characteristic values about ink amounts ejected from all nozzles of the ink jet head, respectively. A decision parameter acquisition unit arranges the characteristic values in the order the nozzles are arranged and calculates a decision parameter from changes in the characteristic values about those of the nozzles, which exit in a predetermined section. A decision unit compares the decision parameter with a predetermined threshold value, thereby determining the density unevenness of the ink jet head.

Abstract: Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.

Abstract: A signal transmission circuit having four lanes includes a constant voltage circuit to generate a constant voltage, a current supply circuit, and differential driver circuits respectively placed for the lanes. The current supply circuit receives a constant voltage from the constant voltage circuit and generates four currents having a value corresponding to a prescribed voltage-current conversion ratio and outputs them in parallel. The differential driver circuits respectively receive the currents output from the current supply circuit and output a voltage having an amplitude corresponding to the prescribed voltage-current conversion ratio. The current supply circuit includes a voltage divider circuit and an analog selector, which form a current supply control circuit capable of changing the voltage-current conversion ratio.

Abstract: An image forming apparatus calculates an ink temperature considering a thermal capacity near nozzles and an ink circulation flow quantity of a circulation pump in addition to an ink temperature when flowing into a recording head and an ink temperature when flowing out of the recording head, and accurately estimates a waste amount of the ink ejected from the nozzles in, e.g., maintenance processing other than image formation.

Abstract: An ink-jet printer of the present invention includes an ink-jet head provided with nozzles for ejecting ink, a downstream tank communicating with the ink-jet head, a pressure pump for producing pressure in the downstream tank to eject ink from the nozzles in a purge operation, a sweep member provided in a maintenance unit, for sweeping away ink and foreign matter remaining around the nozzles after the purge operation, and a control device for keeping the nozzles at a slight positive pressure at the time of ink sweep. Further, the control device produces the slight positive pressure after opening the downstream tank to the atmosphere.

Abstract: According to one embodiment of the present invention, it is possible to realize a signal transmitter which is capable of reducing power consumption and which can be easily designed. A differential transmitter block outputs differential output signals fixed to a predetermined logic signal to a differential receiver block and disconnects terminating resistors from a signal transmission path in an idle state. In the differential receiver block, a differential comparator outputs a logic determined by symbols of the differential output signal from the differential transmitter block, and an operating state detector detects the idle state upon detection that time successively outputting a predetermined logic by the differential comparator reaches a predetermined time, and controls switches so as to disconnect the terminating resistors from the signal transmitter in the receiving side upon detection of the idle state.

Abstract: In a data transmission circuit according to the present invention, selection circuits alternately switch between transistors of a main buffer and transistors of a dummy buffer. In high-speed data transmission, a H/L transmission switch circuit outputs high-speed data to a constant current driver and outputs a selection signal for inputting a control signal to the main buffer to a selection circuit. In low-speed data transmission, on the other hand, the H/L transmission switch circuit outputs a selection signal for inputting a control signal to the main buffer in accordance with the low-speed data to the selection circuit. The H/L transmission switch circuit controls an input of the control signal to the main buffer in accordance with the selection signal.

Abstract: A signal transmission circuit having four lanes includes a constant voltage circuit to generate a constant voltage, a current supply circuit, and differential driver circuits respectively placed for the lanes. The current supply circuit receives a constant voltage from the constant voltage circuit and generates four currents having a value corresponding to a prescribed voltage-current conversion ratio and outputs them in parallel. The differential driver circuits respectively receive the currents output from the current supply circuit and output a voltage having an amplitude corresponding to the prescribed voltage-current conversion ratio. The current supply circuit includes a voltage divider circuit and an analog selector, which form a current supply control circuit capable of changing the voltage-current conversion ratio.

Abstract: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

Abstract: Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided multi-phase clock signals from a counter. The selector receives the parallel data from the register to select one of the data in accordance with a control signal. The counter generates the control signal for the selector so that plural items of data will be output serially from the selector in the sequence in which the plural items data have been serially supplied to the register.

Abstract: Disclosed is a pre-emphasis circuit including a first parallel-to-serial converter, a second parallel-to-serial converter, a mixing circuit and a clock generating circuit. The first parallel-to-serial converter converts parallel data into first serial data, and the second parallel-to-serial converter converts the parallel data into second serial data. The mixing circuit receives the first serial data from the first parallel-to-serial converter and the second serial data from the second parallel-to-serial converter to output a signal emphasizing a change point of the first serial data. The clock generating circuit outputs a first set of clocks made up of clocks having mutually different phases and a second set of clocks made up of clocks having mutually different phases to the first and second parallel-to-serial converters, respectively. The first phase clock of the second set of clocks corresponds to the second phase clock of the first set of clocks.

Abstract: In a data transmission circuit according to the present invention, selection circuits alternately switch between transistors of a main buffer and transistors of a dummy buffer. In high-speed data transmission, a H/L transmission switch circuit outputs high-speed data to a constant current driver and outputs a selection signal for inputting a control signal to the main buffer to a selection circuit. In low-speed data transmission, on the other hand, the H/L transmission switch circuit outputs a selection signal for inputting a control signal to the main buffer in accordance with the low-speed data to the selection circuit. The H/L transmission switch circuit controls an input of the control signal to the main buffer in accordance with the selection signal.

Abstract: A semiconductor interface circuit connected between a first semiconductor device driven by a first level power voltage and a second semiconductor device driven by a second level power voltage which is higher than the first level power voltage. The semiconductor interface circuit includes an output buffer circuit being connected to the first semiconductor device; and at least a depletion type field effect transistor connected between the output buffer circuit and the second semiconductor device, wherein the at least depletion type field effect transistor has a driving capability substantially equal to or near a driving capability of the output buffer circuit.

Abstract: Disclosed is a MOS-type semiconductor integrated circuit, which has: an input circuit section connected to an input pad; an output circuit section connected to an output pat; and an internal circuit section connected between the input circuit section and the output circuit section; wherein the input circuit section includes a first n-channel transistor, a first p-channel transistor and a first protective resistance connected between the first n-channel transistor and the first p-channel transistor, the input pad being connected between the first p-channel transistor and the first protective resistance, the internal circuit section being connected between the first n-channel transistor and the first protective resistance; and the output circuit section includes a second nchannel transistor, a second p-channel transistor and a second protective resistance connected between the second n-channel transistor and the second p-channel transistor, the output pad being connected between the second p-channel transistor