Abstract: A substrate 11 consists of a semiconductor layer 12 as an element formation region and an STI 13 as an isolation region. A gate dielectric 15 is provided on the semiconductor layer 12, and a gate electrode 14 is provided to extend from the top of the gate dielectric 15 to the top of the STI 13. A sidewall 30 for covering the sides of the gate electrode 14 is provided to extend across the top of the semiconductor layer 12 to the tops of regions of the STI 13 adjacent to the outer edges of the semiconductor layer 12. The sidewall 30 is employed as an ion implantation mask for forming high-concentration impurity diffusion layers 16 each serving as a source/drain region.

Abstract: A substrate 11 consists of a semiconductor layer 12 as an element formation region and an STI 13 as an isolation region. A gate dielectric 15 is provided on the semiconductor layer 12, and a gate electrode 14 is provided to extend from the top of the gate dielectric 15 to the top of the STI 13. A sidewall 30 for covering the sides of the gate electrode 14 is provided to extend across the top of the semiconductor layer 12 to the tops of regions of the STI 13 adjacent to the outer edges of the semiconductor layer 12. The sidewall 30 is employed as an ion implantation mask for forming high-concentration impurity diffusion layers 16 each serving as a source/drain region.

Abstract: A semiconductor device comprises varactor regions Va and transistor regions Tr. An active region for a varactor is formed with a substrate contact impurity diffusion region obtained by doping an N well region with N-type impurity at a relatively high concentration. However, any extension region (or LDD region) as in a varactor of a known semiconductor device is not formed in the active region for a varactor. On the other hand, parts of a P well region located to both sides of the polysilicon gate electrode in the transistor region Tr are formed with high-concentration source/drain regions and extension regions. Therefore, the extendable range of a depletion layer is kept wide to extend the capacitance variable range of the varactor.