Patents by Inventor Tadashi Kayada

Tadashi Kayada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7365781
    Abstract: An image signal processor 12 inputs digital picture data 101 into a compressor 13 and into a resolution changer 16 in parallel. The compressor 13 outputs compressed data 102, which is compressed digital picture data 101, to an output 14 through a buffer 17. Meanwhile, a resolution changer 16 outputs the new digital picture data 104, which is the digital picture data 101 with reduced resolution, to the output 14. In accordance with the instruction of a selection signal 108, the output 14 selectively outputs either one of digital picture data 104 with reduced resolution and the buffered compression data 105 as output data 106 through the same signal line at the same signal timing. By this means it is possible to provide a camera apparatus which can simplify circuit configurations of external apparatus that receive digital picture data and compression data and simplify the circuit control.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: April 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Kubota, Tadashi Kayada
  • Patent number: 7317439
    Abstract: Picture quality on a display screen is corrected in accordance with a change either in image information or in the light state. The electronic apparatus includes a display panel, a lighting means for lighting the display panel, a parameter adjusting means for adjusting a parameter participating in picture quality so as to conform the light state while using variations in the light state of the lighting means as a trigger, a signal correcting means for inputting a display signal and correcting the input display signal in accordance with the adjusted parameter, and a driving means for driving the display panel on the basis of the corrected display signal. The light state is controlled according to the content of a file containing the information to be displayed.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: January 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryota Hata, Jun Ikeda, Shuichi Ojima, Tsuyoshi Hirashima, Tadashi Kayada, Kousuke Kubota
  • Patent number: 7023496
    Abstract: In a moving picture decoding display apparatus and moving picture decoding display method according to the present invention, moving picture decoder 101 decodes a moving picture signal, RGB matrix manipulation section 103 converts the decoded video signal in YCbCr format into a video signal in RGB format, contrast/brightness adjusting section 104 adjusts the contrast and brightness of the video signal in RGB format, and liquid crystal display module section 110 displays the adjusted video signal on liquid crystal panel 109. At this point, operation control section 105 switches on and off the operation of RGB matrix manipulation section 103 and contrast/brightness adjusting section 104 corresponding to the actual frame rate in moving picture decoder 101, and only when the operation is “on”, the section 105 controls so that the video signal from contrast/brightness adjusting section 104 is stored in video RAM 107 in liquid crystal display module section 110.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: April 4, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Nagata, Tadashi Kayada
  • Publication number: 20060056715
    Abstract: An image transformation apparatus, image transformation method and recording medium which carries out contraction processing on image data stored in an image memory. For contracting an image, an image transformation apparatus (100) is provided with a contraction work memory (115a) capable of storing an amount of data of one unit block before contraction, a contraction work column memory (115b) capable of storing one column of the unit block and a contraction work line memory (115c) capable of storing data corresponding to one line of the image after contraction.
    Type: Application
    Filed: November 7, 2003
    Publication date: March 16, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoichi Goda, Tadashi Kayada
  • Patent number: 6906756
    Abstract: A vertical region designation circuit 141 outputs a vertical region designation signal to a vertical driver 103 on the basis of vertical display position information, a vertical synchronization signal and a horizontal synchronization signal. A horizontal region designation circuit 142 outputs a horizontal region designation signal to a horizontal driver 102 on the basis of horizontal display position information, a pixel synchronization signal, a vertical synchronization signal and a horizontal synchronization signal. The horizontal driver 102 outputs an input picture signal to a picture display surface 101 from a signal line at a horizontal coordinate corresponding to the number of times of pixel synchronization signals that is counted from an input horizontal synchronization signal as a starting point during a period when a horizontal region designation signal is effective.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 14, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kosuke Kubota, Yutaka Machida, Motoya Miyauchi, Tadashi Kayada, Takeshi Yukitake
  • Publication number: 20050088384
    Abstract: Image de/coding unit 801 decodes coded image data and stores the image data on a temporary basis. Image address bus 123 and image data bus 124 connect image de/coding unit 801 and image display section 901. Image display section 901 stores image data like moving images in frame memory 914 which is a preexisting circuit, and displays the images that are for specified areas and that are produced in image de/coding unit 801 and previously produced images stored in frame memory 914 in overlap. By this means, it is possible to reduce the traffic on MPU (Micro Processor Unit) busses and to present large-volume image data such as moving images by relatively simple additions of functions.
    Type: Application
    Filed: December 14, 2004
    Publication date: April 28, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tadashi Kayada, Yutaka Machida, Takeshi Yukitake, Hiroyuki Ito, Kosuke Kubota, Koji Abe, Yoji Fujiwara
  • Patent number: 6831617
    Abstract: A control section 130 for outputting a selection signal for selecting the display areas of the display section 110 and transferring display data classified in response to the display areas and the display type to both or either of a display data processing section A 140 and a display data processing section B 133, the display data processing section A 140 and the display data processing section B 133 for converting the display data into a format fitted for the display area and the display type, a data transfer path 160 for separately transferring data from the display data processing section A 140 to the display section 110, and a data transfer path 170 for separately transferring data from the display data processing section B 133 to the display section 110, wherein images of the display data generated by the display data processing section A 140 and the display data processing section B 133 of the display section 110 are selectively displayed in the display area of the display section 110 based on the selec
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: December 14, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Motoya Miyauchi, Yutaka Machida, Tadashi Kayada, Kosuke Kubota
  • Publication number: 20040119718
    Abstract: An image processing apparatus that prevents data traffic from expanding and expands the function without changing existing peripheral devices. An image generated by a DSP (110) is output to a liquid crystal interface (130) and an image generated by an image processor (400) is output to a liquid crystal interface (410). Then, an MPU (100) controls an image output switching section (150) and the image output switching section (150) controls a gate (140) and a gate (420) and a synchronizing signal and an image generated by the DSP (110) or image processor (400) are output to a driver (600) of a liquid crystal module. Then, the driver (600) drives a liquid crystal panel (610) and the image is displayed on the liquid crystal panel (610).
    Type: Application
    Filed: December 16, 2003
    Publication date: June 24, 2004
    Inventor: Tadashi Kayada
  • Publication number: 20030151671
    Abstract: An image signal processor 12 inputs digital picture data 101 into a compressor 13 and into a resolution changer 16 in parallel. The compressor 13 outputs compressed data 102, which is compressed digital picture data 101, to an output 14 through a buffer 17. Meanwhile, a resolution changer 16 outputs the new digital picture data 104, which is the digital picture data 101 with reduced resolution, to the output 14. In accordance with the instruction of a selection signal 108, the output 14 selectively outputs either one of digital picture data 104 with reduced resolution and the buffered compression data 105 as output data 106 through the same signal line at the same signal timing. By this means it is possible to provide a camera apparatus which can simplify circuit configurations of external apparatus that receive digital picture data and compression data and simplify the circuit control.
    Type: Application
    Filed: December 26, 2002
    Publication date: August 14, 2003
    Inventors: Kosuke Kubota, Tadashi Kayada
  • Publication number: 20030076886
    Abstract: In a moving picture decoding display apparatus and moving picture decoding display method according to the present invention, moving picture decoder 101 decodes a moving picture signal, RGB matrix manipulation section 103 converts the decoded video signal in YCbCr format into a video signal in RGB format, contrast/brightness adjusting section 104 adjusts the contrast and brightness of the video signal in RGB format, and liquid crystal display module section 110 displays the adjusted video signal on liquid crystal panel 109. At this point, operation control section 105 switches on and off the operation of RGB matrix manipulation section 103 and contrast/brightness adjusting section 104 corresponding to the actual frame rate in moving picture decoder 101, and only when the operation is “on”, the section 105 controls so that the video signal from contrast/brightness adjusting section 104 is stored in video RAM 107 in liquid crystal display module section 110.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 24, 2003
    Inventors: Hideki Nagata, Tadashi Kayada
  • Publication number: 20020190943
    Abstract: Image de/coding unit 801 decodes coded image data and stores the image data on a temporary basis. Image address bus 123 and image data bus 124 connect image de/coding unit 801 and image display section 901. Image display section 901 stores image data like moving images in frame memory 914 which is a preexisting circuit, and displays the images that are for specified areas and that are produced in image de/coding unit 801 and previously produced images stored in frame memory 914 in overlap. By this means, it is possible to reduce the traffic on MPU (Micro Processor Unit) busses and to present large-volume image data such as moving images by relatively simple additions of functions.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 19, 2002
    Inventors: Tadashi Kayada, Yutaka Machida, Takeshi Yukitake, Hiroyuki Ito, Kosuke Kubota, Koji Abe, Yoji Fujiwara
  • Publication number: 20020149595
    Abstract: A decoding section 111 decodes inputted coded data to image data and outputs it to an image data writing section 112 whenever necessary. The decoding section 111 outputs a decode completion notice signal to an image data reading section 114 and control signal generating section 115 every time when outputting a predetermined amount of image data (for example, an amount corresponding to one frame). The image data writing section 112 writes image data to the storing section 113 whenever necessary. An image data reading section 114 operates intermittently with timing when the decode completion notice signal is input thereto, and reads a predetermined amount of image data from the storage section 113. The control signal generating section 115 generates a control signal 206 that instructs a new portion in image data decoded by decoding means.
    Type: Application
    Filed: April 16, 2002
    Publication date: October 17, 2002
    Inventors: Kosuke Kubota, Hideki Nagata, Tadashi Kayada, Yutaka Machida, Takeshi Yukitake
  • Publication number: 20020105527
    Abstract: Picture quality on a display screen is corrected in accordance with a change either in image information or in the light state. The electronic apparatus includes a display panel, a lighting means for lighting the display panel, a parameter adjusting means for adjusting a parameter participating in picture quality so as to conform the light state while using variations in the light state of the lighting means as a trigger, a signal correcting means for inputting a display signal and correcting the input display signal in accordance with the adjusted parameter, and a driving means for driving the display panel on the basis of the corrected display signal. The light state is controlled according to the content of a file containing the information to be displayed.
    Type: Application
    Filed: October 25, 2001
    Publication date: August 8, 2002
    Inventors: Ryota Hata, Jun Ikeda, Shuichi Ojima, Tsuyoshi Hirashima, Tadashi Kayada, Kousuke Kubota
  • Patent number: 5719906
    Abstract: A signal generating apparatus generates four sets of signals whose rising timing and falling timing are controlled. One signal among the four signals is produced by employing a first sequence control unit, a first coincidence detecting unit, a second coincidence detecting unit, and a first output controlling unit. A timer increments a count value in response to a timer increment signal to produce a timer output value. The first sequence controlling unit produces two correction values obtained by correcting the timer output value inputted from the timer. The first coincidence detecting unit outputs a coincidence detection pulse when the correction value inputted from the first sequence control unit is coincident with the internally set set value. The second coincidence detecting unit outputs another coincidence detection pulse when the correction value inputted from the first sequence control unit is coincident with the internally set set value.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: February 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tadashi Kayada