Patents by Inventor Tadashi Kodaira
Tadashi Kodaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10290570Abstract: A wiring substrate includes a first substrate and a second substrate stacked on the first substrate. The first substrate includes a first adhesive layer and conductive paste. The first adhesive layer is on a surface of a first insulating layer. The conductive paste is in an opening in the first adhesive layer. The second substrate includes a second adhesive layer and a protruding electrode. The second adhesive layer is on a surface of a second insulating layer facing toward the first substrate, and is bonded to the first adhesive layer. The protruding electrode has an end uncovered by the second adhesive layer, and is electrically connected to the conductive paste.Type: GrantFiled: January 10, 2018Date of Patent: May 14, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Tadashi Arai, Yoshikazu Hirabayashi, Hidetoshi Arai, Tadashi Kodaira
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Patent number: 10121695Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip, conductive paste, and an adhesive layer. The wiring substrate includes an insulating layer and a wiring layer on a surface of the insulating layer. The semiconductor chip includes a circuit-formation surface in which an electrode pad is provided, and is mounted on the wiring substrate with the circuit-formation surface facing toward the wiring layer. The conductive paste electrically connects the wiring layer and the electrode pad. The adhesive layer is over the entirety of the surface of the insulating layer, and covers the wiring layer and the conductive paste. The adhesive layer fills in a gap between the surface of the insulating layer and the circuit-formation surface, to bond the wiring substrate and the semiconductor chip. The adhesive layer extends onto a side surface of the semiconductor chip to form a fillet.Type: GrantFiled: December 22, 2017Date of Patent: November 6, 2018Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Tadashi Arai, Yoshikazu Hirabayashi, Hidetoshi Arai, Tadashi Kodaira
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Publication number: 20180218972Abstract: A wiring substrate includes a first substrate and a second substrate stacked on the first substrate. The first substrate includes a first adhesive layer and conductive paste. The first adhesive layer is on a surface of a first insulating layer. The conductive paste is in an opening in the first adhesive layer. The second substrate includes a second adhesive layer and a protruding electrode. The second adhesive layer is on a surface of a second insulating layer facing toward the first substrate, and is bonded to the first adhesive layer. The protruding electrode has an end uncovered by the second adhesive layer, and is electrically connected to the conductive paste.Type: ApplicationFiled: January 10, 2018Publication date: August 2, 2018Inventors: Tadashi ARAI, Yoshikazu HIRABAYASHI, Hidetoshi ARAI, Tadashi KODAIRA
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Publication number: 20180218941Abstract: A semiconductor device includes a wiring substrate, a semiconductor chip, conductive paste, and an adhesive layer. The wiring substrate includes an insulating layer and a wiring layer on a surface of the insulating layer. The semiconductor chip includes a circuit-formation surface in which an electrode pad is provided, and is mounted on the wiring substrate with the circuit-formation surface facing toward the wiring layer. The conductive paste electrically connects the wiring layer and the electrode pad. The adhesive layer is over the entirety of the surface of the insulating layer, and covers the wiring layer and the conductive paste. The adhesive layer fills in a gap between the surface of the insulating layer and the circuit-formation surface, to bond the wiring substrate and the semiconductor chip. The adhesive layer extends onto a side surface of the semiconductor chip to form a fillet.Type: ApplicationFiled: December 22, 2017Publication date: August 2, 2018Inventors: Tadashi ARAI, Yoshikazu HIRABAYASHI, Hidetoshi ARAI, Tadashi KODAIRA
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Patent number: 7873245Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: December 20, 2007Date of Patent: January 18, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Patent number: 7807560Abstract: A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic sticking layer forming step of causing a solution containing the tackifying compound to chemically react to the metal film, thereby forming an organic sticking layer on the metal film, and a conductive ball mounting step of supplying the conductive ball on the pads having the organic sticking layer formed thereon, thereby mounting the conductive ball on the pads through the metal film.Type: GrantFiled: July 16, 2008Date of Patent: October 5, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Masao Nakazawa, Masaki Sanada, Sachiko Oda, Tadashi Kodaira, Kinji Nagata, Masaru Yamazaki, Kenjiro Enoki
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Patent number: 7801396Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: December 20, 2007Date of Patent: September 21, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Publication number: 20100155933Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Applicant: Shinko ElectronicsInventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Publication number: 20100155114Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: February 24, 2010Publication date: June 24, 2010Applicant: Shinko ElectronicsInventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Patent number: 7696617Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: GrantFiled: August 28, 2007Date of Patent: April 13, 2010Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Publication number: 20090288870Abstract: A method of manufacturing a wiring substrate of the present invention, includes a step of forming a first wiring layer on an underlying layer, a step of forming a stacked body in which a protection layer is provided on an insulating layer, on the first wiring layer, a step of forming a via hole reaching the first wiring layer by processing the protection layer and the insulating layer, a step of roughening a side surface of the via hole by applying a desmear process to an inside of the via hole while using the protection layer as a mask, a step of removing the protection layer, and a step of forming a second wiring layer, which is connected to the first wiring layer via the via hole, on the insulating layer. The second wiring layer may be formed after the surface of the insulating layer is roughened, or the second wiring layer may be formed without roughening of the surface of the insulating layer.Type: ApplicationFiled: May 21, 2009Publication date: November 26, 2009Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hitoshi KONDO, Tomoyuki Shimodaira, Tadashi Kodaira
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Publication number: 20090023281Abstract: A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic sticking layer forming step of causing a solution containing the tackifying compound to chemically react to the metal film, thereby forming an organic sticking layer on the metal film, and a conductive ball mounting step of supplying the conductive ball on the pads having the organic sticking layer formed thereon, thereby mounting the conductive ball on the pads through the metal film.Type: ApplicationFiled: July 16, 2008Publication date: January 22, 2009Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Imafuji, Masao Nakazawa, Masaki Sanada, Sachiko Oda, Tadashi Kodaira, Kinji Nagata, Masaru Yamazaki, Kenjiro Enoki
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Publication number: 20080251496Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: ApplicationFiled: December 20, 2007Publication date: October 16, 2008Applicant: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Publication number: 20080107375Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: ApplicationFiled: December 20, 2007Publication date: May 8, 2008Applicant: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Patent number: 7340121Abstract: An optoelectric composite substrate of the present invention includes an insulating film, an optical waveguide embedded in the insulating film in a state that an upper surface is exposed from the insulating film, a via hole formed to pass through the insulating film, a conductor formed in the via hole, and a connection terminal on which an optical device is mounted and which is connected to an upper end side of the conductor, wherein the connection terminal is embedded in an upper-side portion of the via hole or is projected from the insulating film.Type: GrantFiled: February 22, 2005Date of Patent: March 4, 2008Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideki Yonekura, Tadashi Kodaira
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Publication number: 20080042258Abstract: To prevent or alleviate the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package for mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a low strength. A package for semiconductor devices is formed as a laminate of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon the other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole region or some region(s) of the insulating resin layers of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: ApplicationFiled: August 28, 2007Publication date: February 21, 2008Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Patent number: 7285856Abstract: To prevent the occurrence of stress in the junction portion between the semiconductor element and the semiconductor package mounting the semiconductor element, so that cracks will not occur even when there is mounted a semiconductor element having a small strength. A package for semiconductor devices is formed as a laminate (20) of many layers including a plurality of conducting layers and insulating resin layers that are alternately laminated one upon other and having, on one surface of the laminate, a portion for mounting a semiconductor element. The whole regions or some regions of the insulating resin layers (20d to 20f) of the laminate, including at least the portion for mounting the semiconductor element and the peripheries thereof, are constituted by a prepreg obtained by impregnating a woven fabric of a liquid crystal polymer with an insulating resin.Type: GrantFiled: May 28, 2004Date of Patent: October 23, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kazuhiko Ooi, Tadashi Kodaira, Eisaku Watari, Jyunichi Nakamura, Shunichiro Matsumoto
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Patent number: 7196426Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: GrantFiled: November 24, 2004Date of Patent: March 27, 2007Assignee: Shinko Electric Industries Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Patent number: 7164198Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.Type: GrantFiled: August 28, 2003Date of Patent: January 16, 2007Assignee: Shinko Electric Industres, Co., Ltd.Inventors: Jyunichi Nakamura, Tadashi Kodaira, Shunichiro Matsumoto, Hironari Aratani, Takanori Tabuchi, Takeshi Chino
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Patent number: 7093356Abstract: A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.Type: GrantFiled: September 15, 2003Date of Patent: August 22, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe