Patents by Inventor Tadashi Kuramoto

Tadashi Kuramoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor integrated circuit device
    Patent number: 5512497
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: April 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
  • Method of manufacturing semiconductor integrated circuit device
    Patent number: 5354699
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: October 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
  • Semiconductor integrated circuit device
    Patent number: 5057894
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: May 23, 1990
    Date of Patent: October 15, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto