Abstract: An edaravone suspension for human oral administration includes edaravone particles, a dispersant, and water.

Abstract: The present invention provides a peptide that consists of an amino acid sequence with 20 or fewer residues containing at least one amino acid sequence selected from the group consisting of the amino acid sequence represented in SEQ ID NO: 1, the amino acid sequence represented in SEQ ID NO: 2 and the amino acid sequence represented in SEQ ID NO: 38, the peptide having an activity to inhibit proliferation of a tumor cell or having an activity to inhibit binding between an epidermal growth factor receptor and a signal-transducing adaptor family member-2 (STAP-2); a peptide with a cell-penetrating peptide added to a terminus of the above peptide with or without a linker sequence interposed between the cell-penetrating peptide and the terminus; and pharmaceutical compositions containing any of these peptides.

Abstract: The present invention provides a compound represented by General Formula (1) or (1?) [in the formula, R1 and R2 each independently represents a hydrogen atom or a hydroxy group; R3 represents an alkyl group having 1 to 6 carbon atoms; R4 represents a halogen atom or an alkyl group; m indicates the number of R4 and represents an integer of 0 to 4; in a case where m is 2 or more, a plurality of R4's may be the same or different from each other; n represents an integer of 1 to 6; and n? represents an integer of 1 to 4] and a neutrophil infiltration suppressor containing the compound as an active ingredient.

Abstract: According to one embodiment, a power semiconductor device includes first and second electrodes, first, second, third, and fourth semiconductor layers, a first control electrode, and a first insulating film. The first semiconductor layer is provided on the first electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the first semiconductor layer to be separated from the second semiconductor layer. The fourth semiconductor layer is provided on the third semiconductor layer. The second electrode is provided on the fourth semiconductor layer. The first control electrode is provided between the second and third semiconductor layers to be shifted toward the third semiconductor layer. The first insulating film is provided between the first semiconductor layer and the first control electrode, between the second semiconductor layer and the first control electrode, and between the third semiconductor layer and the first control electrode.

Abstract: According to one embodiment, an IGBT region includes: a collector layer of a first conductivity type, a drift layer of a second conductivity type, a body layer of the first conductivity type, and a second electrode extending to the drift layer and the body layer via a first insulating film in a stacking direction of a first electrode and the collector layer. A diode region includes: a cathode layer of the second conductivity type, the drift layer, an anode layer of the first conductivity type, and a conductive layer extending to the drift layer and the anode layer via a second insulating film in the stacking direction. The second electrode and the conductive layer are separated from one another at a predetermined distance.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first electrode, a second semiconductor region of the first conductivity type and a second electrode. The first semiconductor region includes a first portion including a first major surface and a second portion extending in a first direction perpendicular to the first major surface on the first major surface. The first electrode includes a third portion provided to face the second portion and is provided to be separated from the first semiconductor region. The second semiconductor region is provided between the second and third portions, includes a first concentration region having a lower impurity concentration than the first semiconductor region and forms a Schottky junction with the third portion. The second electrode is provided on an opposite side of the first major surface and in conduction with the first portion.

Abstract: According to one embodiment, an electronic device includes: a casing; and an operating module exposed on an external surface of the casing at a nearer side than a keyboard in a depth direction of the casing, the operating module including a pointer operating module receiving an operation to move a pointer on a screen, a first click operating module receiving a click operation associated with a position of the pointer, and a second click operating module receiving a click operation associated with the position of the pointer, wherein among the pointer operating module, and the first and second click operating modules, the pointer operating module is t a nearest side in the depth direction, the first click operating module is at a farther side than the pointer operating module, and the second click operating module is at a farther side than the first click operating module in the depth direction.

Abstract: According to one embodiment, an information processing apparatus includes a memory unit which stores attribute information which indicates a characteristic quantity of each of components constituting a product, and parent-child relationship information which indicates a parent-child relationship between the components, a unit which calculates positions on a tree diagram of nodes corresponding to the components, a unit which calculates, for each of the components, a sum of the characteristic quantity of the component and the characteristic quantities of all child components belonging to the component, a unit which determines, for each of the nodes, a mode of a branch line which is to connect the node to a parent node thereof, based on the sum calculated for each of the components, and a unit which creates the tree diagram based on the calculated positions of the nodes and the determined mode of the branch line corresponding to each node.

Abstract: According to one embodiment, an image display control system includes a transmitting-side information processing device comprising shared data and a receiving-side information processing device viewing the shared data via a network. The transmitting-side information processing device further comprises transmission means for, upon receiving an access from the receiving-side information processing device, transmitting list information of the shared data and local time information in a location where the transmitting-side information processing device is provided, to the receiving-side information processing device making the access. The receiving-side information processing device includes storage means for storing time-corresponding data, and display means for associating the time-corresponding data which are read with the received list information of the shared data, and displaying the shared data together with the time-corresponding data.

Abstract: According to one embodiment, an information processing apparatus includes a memory unit which stores attribute information which indicates a characteristic quantity of each of components constituting a product, and parent-child relationship information which indicates a parent-child relationship between the components, a unit which calculates positions on a tree diagram of nodes corresponding to the components, a unit which calculates, for each of the components, a sum of the characteristic quantity of the component and the characteristic quantities of all child components belonging to the component, a unit which determines, for each of the nodes, a mode of a branch line which is to connect the node to a parent node thereof, based on the sum calculated for each of the components, and a unit which creates the tree diagram based on the calculated positions of the nodes and the determined mode of the branch line corresponding to each node.

Abstract: A semiconductor device includes a trench gate IGBT and a MISFET. The IGBT has an auxiliary base layer which is formed in an arbitrary region between two adjacent trenches and is insulated from an emitter electrode of the IGBT, and a carrier discharge electrode which contacts a surface of the auxiliary base layer. The MISFET is connected to the emitter electrode and the carrier discharge electrode and turned on upon turning off the IGBT. Upon turning off the IGBT, the accumulated carriers below the auxiliary base layer are discharged to the emitter electrode via the auxiliary base layer, the carrier discharge electrode, and the MISFET. This promotes the carrier discharge effect in turn-off, realizing a high-speed turn-off characteristic.

Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.

Abstract: According to the present invention, there is provided a semiconductor device including a trench gate IGBT, having: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type which is formed on one surface of the first semiconductor layer; a base layer of the first conductivity type which is formed in a surface portion of the second semiconductor layer; emitter layers of the second conductivity type which are selectively formed in a surface portion of the base layer; a plurality of trenches which extend through the emitter layers and the base layer and are formed to a predetermined depth in the second semiconductor layer; gate electrodes which are formed on gate insulating films in the trenches; an emitter electrode which is formed on the emitter layers and the base layer; a collector electrode which is formed on the other surface of the first semiconductor layer; an auxiliary base layer of the first conductivity type which is formed in an arbitrary reg

Abstract: The power semiconductor device includes a plurality of trenches disposed in a surface of a semiconductor active layer to reach a first base layer of a first conductivity type. The trenches are disposed at intervals to partition a main cell and a dummy cell. In the main cell, a second base layer of a second conductivity type and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode and gate insulating film are disposed in each trench. A partition structure is disposed in the surface of the semiconductor active layer to electrically isolate the buffer layer from the emitter electrode.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: A semiconductor device in accordance with present invention includes a first conduction type first semiconductor layer; a second conduction type second semiconductor layer which is formed on the first semiconductor layer and has a substantially uniform impurity concentration; a plurality of first conduction type base layers formed in the surface of the second semiconductor layer; a plurality of second conduction type emitter layers formed in the surfaces of the respective base layers; channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer; a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between two base layers adjacent to each other; a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions; an emitter electrode connected to the base layers and the emitter layers; and a

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.

Abstract: A semiconductor device in accordance with present invention includes a first conduction type first semiconductor layer; a second conduction type second semiconductor layer which is formed on the first semiconductor layer and has a substantially uniform impurity concentration; a plurality of first conduction type base layers formed in the surface of the second semiconductor layer; a plurality of second conduction type emitter layers formed in the surfaces of the respective base layers; channel regions formed in the surfaces of the respective base layers and between the emitter layers and the second semiconductor layer; a first conduction type auxiliary base layer formed in the surface of the second semiconductor layer between two base layers adjacent to each other; a gate electrode formed via a gate insulating film on the second semiconductor layer between the auxiliary base layer and the two base layers and on the channel regions; an emitter electrode connected to the base layers and the emitter layers; and a

Abstract: An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type formed on a top surface of the first semiconductor layer, a base layer of the first conductivity type formed on a top surface of the second semiconductor layer, a plurality of gate electrodes each of which is buried in a trench with a gate insulation film interposed therebetween, the trench being formed in the base layer to a depth reaching said second semiconductor layer from a surface of the base layer, each the gate electrode having an upper surface of a rectangular pattern with different widths in two orthogonal directions, the gate electrodes being disposed in a direction along a short side of the rectangular pattern, and emitter layers of the second conductivity type formed in the surface of the base layer to oppose both end portions of each the gate electrode in a direction along a long side of the rectangular pattern.