Patents by Inventor Tadashi Matsuoka
Tadashi Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170174454Abstract: A sheet conveyance apparatus includes: a placement part configured such that stacked sheets are disposed on the placement part; a housing including an open/close part and accommodating the placement part, at least a portion of the open/close part being configured to be opened and closed; and a suction unit connected with the housing, and configured to draw gas from an interior of the housing.Type: ApplicationFiled: December 12, 2016Publication date: June 22, 2017Inventors: Tadashi MATSUOKA, Yasuo NIIKURA, Yousuke EDO, Satoru TAKANO, Yasunori HINO, Atsunori YOSHIDA, Ryo KANNO, Hikaru FUKASAWA
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Publication number: 20170174453Abstract: A sheet-material supply device includes a lift, a sheet-material detector, and a sheet-material retaining conveyor. The lift elevates sheet materials in a stacked state. The sheet-material detector detects that an uppermost sheet material of the sheet materials in the stacked state has reached a predetermined height. The sheet-material retaining conveyor retains and conveys the uppermost sheet material that has reached the predetermined height. The sheet-material supply device stops elevation of the sheet materials in the stacked state when the sheet-material detector detects that the uppermost sheet material has reached the predetermined height. The sheet-material retaining conveyor is disposed to be movable in a direction in which the sheet materials in the stacked state elevate.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Inventors: Takeshi AKAI, Hidehiko FUJIWARA, Yasuo NIIKURA, Yousuke EDO, Satoru TAKANO, Yasunori HINO, Tadashi MATSUOKA, Atsunori YOSHIDA, Ryo KANNO, Hikaru FUKASAWA
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Publication number: 20170174462Abstract: A stacking apparatus includes a conveyance unit, a stacking unit, and a separation member supply unit. The conveyance unit conveys sheets for circuit board. The stacking unit stacks the sheets. The separation member supply unit supplies a separation member to separate the stacked sheets at any position. The separation member supply unit places the separation member on the sheet in being conveyed.Type: ApplicationFiled: December 9, 2016Publication date: June 22, 2017Inventors: Yousuke EDO, Yasufumi TAKAHASHI, Yasuo NIIKURA, Satoru TAKANO, Hidehiko FUJIWARA, Takeshi AKAI, Yasunori HINO, Tadashi MATSUOKA, Atsunori YOSHIDA, Ryo KANNO, Hikaru FUKASAWA, Hiroshi KOMURO, Masaru YAMAGISHI, Toshihiro SHIMADA, Satoshi AIZAWA, Kenji ISHII
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Patent number: 9685911Abstract: In a power amplifier module for performing slope control of a transmitting signal, a gain variation due to a variation in battery voltage is suppressed while suppressing an increase in circuit size. The power amplifier module includes: a first regulator for outputting a first voltage corresponding to a control voltage for controlling a signal level; a second regulator for outputting a second voltage that rises as a battery voltage drops; a first amplifier supplied with the first voltage as a power-supply voltage to amplify an input signal and output an amplified signal; and a second amplifier for amplifying the amplified signal, wherein the second amplifier includes a first amplification unit supplied with the second voltage as the power-supply voltage to amplify the amplified signal, and a second amplification unit supplied with the battery voltage as the power-supply voltage to amplify the amplified signal.Type: GrantFiled: August 20, 2015Date of Patent: June 20, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Takayuki Tsutsui, Tadashi Matsuoka, Satoshi Tanaka
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Patent number: 9559654Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.Type: GrantFiled: October 22, 2014Date of Patent: January 31, 2017Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
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Publication number: 20160308575Abstract: Provided is a high frequency module capable of reducing the IMD. During the transmission/reception operation based on W-CDMA, control signals VSWCC, VTRXCC are output as Hi signals from a control logic. Consequently, transistor T1 is turned ON, and transistors T2, T3 are respectively turned OFF. When the transistor T1 is turned ON, the voltage output from an operational amplifier is output as the signal VVSW to a control terminal, and the control signal VTRXC is output as a Hi signal. The signal VVSW is of a voltage level that is lower than that of the control signal VTRXC. The control signal VTRXC is a signal for turning ON a transistor circuit Q1, and the signal VVSW is a signal for supplying a DC voltage to the antenna potential. It is thereby possible to reduce the ON resistance of the transistor circuit Q1 and improve the IMD characteristics.Type: ApplicationFiled: June 30, 2016Publication date: October 20, 2016Inventors: Hayato NAKAMURA, Eigo TANGE, Tadashi MATSUOKA, Yasushi SHIGENO
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Publication number: 20160285423Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.Type: ApplicationFiled: June 10, 2016Publication date: September 29, 2016Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
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Patent number: 9436204Abstract: A band-gap referenced voltage circuit with smaller parasitic resistance which brings reduced band-gap error is disclosed. This reduced error stems from the unique configuration of stacked diode and a shorter wiring line to a resistor. The band-gap referenced voltage circuit includes two diodes, an operational amplifier with non-inverting and inverting inputs and an output for the band-gap voltage output, and three resistors. Employing the stacked configuration of the diode with the top anode electrode, the wiring line which connects the non-inverting input of the operational amplifier and the voltage reference diode is made short. Then the resistance of the wiring line, called also parasitic resistance, would be small.Type: GrantFiled: August 3, 2015Date of Patent: September 6, 2016Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Terukazu Nagakura, Tadashi Matsuoka, Fuminori Morisawa
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Patent number: 9413415Abstract: Provided is a high frequency module capable of reducing the IMD. During the transmission/reception operation based on W-CDMA, control signals VSWCC, VTRXCC are output as Hi signals from a control logic. Consequently, transistor T1 is turned ON, and transistors T2, T3 are respectively turned OFF. When the transistor T1 is turned ON, the voltage output from an operational amplifier is output as the signal VVSW to a control terminal, and the control signal VTRXC is output as a Hi signal. The signal VVSW is of a voltage level that is lower than that of the control signal VTRXC. The control signal VTRXC is a signal for turning ON a transistor circuit Q1, and the signal VVSW is a signal for supplying a DC voltage to the antenna potential. It is thereby possible to reduce the ON resistance of the transistor circuit Q1 and improve the IMD characteristics.Type: GrantFiled: December 14, 2012Date of Patent: August 9, 2016Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Hayato Nakamura, Eigo Tange, Tadashi Matsuoka, Yasushi Shigeno
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Patent number: 9397618Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.Type: GrantFiled: March 6, 2015Date of Patent: July 19, 2016Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
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Publication number: 20160072445Abstract: In a power amplifier module for performing slope control of a transmitting signal, a gain variation due to a variation in battery voltage is suppressed while suppressing an increase in circuit size. The power amplifier module includes: a first regulator for outputting a first voltage corresponding to a control voltage for controlling a signal level; a second regulator for outputting a second voltage that rises as a battery voltage drops; a first amplifier supplied with the first voltage as a power-supply voltage to amplify an input signal and output an amplified signal; and a second amplifier for amplifying the amplified signal, wherein the second amplifier includes a first amplification unit supplied with the second voltage as the power-supply voltage to amplify the amplified signal, and a second amplification unit supplied with the battery voltage as the power-supply voltage to amplify the amplified signal.Type: ApplicationFiled: August 20, 2015Publication date: March 10, 2016Inventors: Takayuki TSUTSUI, Tadashi MATSUOKA, Satoshi TANAKA
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Publication number: 20160062382Abstract: A band-gap referenced voltage circuit with smaller parasitic resistance which brings reduced band-gap error is disclosed. This reduced error stems from the unique configuration of stacked diode and a shorter wiring line to a resistor. The band-gap referenced voltage circuit includes two diodes, an operational amplifier with non-inverting and inverting inputs and an output for the band-gap voltage output, and three resistors. Employing the stacked configuration of the diode with the top anode electrode, the wiring line which connects the non-inverting input of the operational amplifier and the voltage reference diode is made short. Then the resistance of the wiring line, called also parasitic resistance, would be small.Type: ApplicationFiled: August 3, 2015Publication date: March 3, 2016Inventors: Terukazu Nagakura, Tadashi Matsuoka, Fuminori Morisawa
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Publication number: 20150270809Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.Type: ApplicationFiled: March 6, 2015Publication date: September 24, 2015Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
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Publication number: 20150130537Abstract: Disclosed is a power amplification module which has a comparatively small size and is capable of adjusting the rising characteristic of a gain. The power amplification module includes a first gain control current generation circuit which generates a first gain control current changing with a control voltage, a first bias current generation circuit which generates a first bias current according to the first gain control current, a gain control voltage generation circuit which generates a gain control voltage changing with the control voltage, a first transistor which is emitter-grounded and in which an input signal and the first bias current are supplied to a base thereof, and a second transistor which is cascode-connected to the first transistor and in which the gain control voltage is supplied to a base thereof and a first output signal obtained by amplifying the input signal is output from a collector thereof.Type: ApplicationFiled: October 22, 2014Publication date: May 14, 2015Inventors: Hayato Nakamura, Mitsuo Ariie, Tadashi Matsuoka, Tsutomu Onaro
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Publication number: 20140370827Abstract: Provided is a high frequency module capable of reducing the IMD. During the transmission/reception operation based on W-CDMA, control signals VSWCC, VTRXCC are output as Hi signals from a control logic. Consequently, transistor T1 is turned ON, and transistors T2, T3 are respectively turned OFF. When the transistor T1 is turned ON, the voltage output from an operational amplifier is output as the signal VVSW to a control terminal, and the control signal VTRXC is output as a Hi signal. The signal VVSW is of a voltage level that is lower than that of the control signal VTRXC. The control signal VTRXC is a signal for turning ON a transistor circuit Q1, and the signal VVSW is a signal for supplying a DC voltage to the antenna potential. It is thereby possible to reduce the ON resistance of the transistor circuit Q1 and improve the IMD characteristics.Type: ApplicationFiled: December 14, 2012Publication date: December 18, 2014Inventors: Hayato Nakamura, Eigo Tange, Tadashi Matsuoka, Yasushi Shigeno
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Patent number: 8898312Abstract: A terminal allows immediate receipt of notification, while holding down the load on a management control device. The terminal has a timer value storage for storing a timer value, a counter for counting the cycle indicated by the timer value, a connection request part for transmitting a connection request to the management control device every time when the counting is finished, an event detector for detecting an event, and a timer value modifier for modifying the timer value to a value indicating a shorter cycle, upon occurrence of the event. The connection request part further transmits the connection request to the management control device, upon occurrence of detecting the event, and the timer value modifier modifies the timer value a value indicating a longer cycle, upon receiving a message indicating that there is no processing request from the management control device.Type: GrantFiled: November 14, 2011Date of Patent: November 25, 2014Assignee: Hitachi, Ltd.Inventors: Miho Kondo, Masaki Nakano, Tadashi Matsuoka
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Patent number: 8868008Abstract: A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.Type: GrantFiled: July 12, 2011Date of Patent: October 21, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoshi Tanaka, Tadashi Matsuoka, Masanori Iijima, Yasushi Shigeno
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Patent number: 8546980Abstract: There is provided a radio-frequency module and a radio communication system capable of supporting multiple bands at low cost or small size. A high-frequency power amplifier device includes a power amplifier circuit unit for GSM and a control circuit outputting antenna switch control signals with a VSW1 level or a VSW2 level in response to a mode setting signal for selecting GSM or W-CDMA. The VSW2 level is generated by boosting the VSW1 level using a clock signal from an oscillation circuit. When GSM is selected by the mode setting signal, the high-frequency power amplifier device stops the oscillation circuit and outputs the antenna switch control signals of the VSW1 level to an antenna switch device. When W-CDMA is selected by the mode setting signal, the high-frequency power amplifier device outputs the antenna switch control signals of the VSW2 level to the antenna switch device, using the oscillation circuit.Type: GrantFiled: December 8, 2011Date of Patent: October 1, 2013Assignee: Renesas Electronics CorporationInventors: Kenichi Shimamoto, Yoshiaki Harasawa, Tadashi Matsuoka
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Publication number: 20120163247Abstract: There is provided a radio-frequency module and a radio communication system capable of supporting multiple bands at low cost or small size. A high-frequency power amplifier device includes a power amplifier circuit unit for GSM and a control circuit outputting antenna switch control signals with a VSW1 level or a VSW2 level in response to a mode setting signal for selecting GSM or W-CDMA. The VSW2 level is generated by boosting the VSW1 level using a clock signal from an oscillation circuit. When GSM is selected by the mode setting signal, the high-frequency power amplifier device stops the oscillation circuit and outputs the antenna switch control signals of the VSW1 level to an antenna switch device. When W-CDMA is selected by the mode setting signal, the high-frequency power amplifier device outputs the antenna switch control signals of the VSW2 level to the antenna switch device, using the oscillation circuit.Type: ApplicationFiled: December 8, 2011Publication date: June 28, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi SHIMAMOTO, Yoshiaki HARASAWA, Tadashi MATSUOKA
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Publication number: 20120124221Abstract: A terminal allows immediate receipt of notification, while holding down the load on a management control device. The terminal has a timer value storage for storing a timer value, a counter for counting the cycle indicated by the timer value, a connection request part for transmitting a connection request to the management control device every time when the counting is finished, an event detector for detecting an event, and a timer value modifier for modifying the timer value to a value indicating a shorter cycle, upon occurrence of the event. The connection request part further transmits the connection request to the management control device, upon occurrence of detecting the event, and the timer value modifier modifies the timer value a value indicating a longer cycle, upon receiving a message indicating that there is no processing request from the management control device.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Inventors: Miho KONDO, Masaki Nakano, Tadashi Matsuoka