Patents by Inventor Tadashi Matsushima

Tadashi Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8981975
    Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2?. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimi Iso, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Patent number: 8614636
    Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2n. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: December 24, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimi Iso, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Publication number: 20120062403
    Abstract: In AD conversion of a voltage, data continuity is ensured between the results of conversion after amplification and of direct conversion without amplification. In AD conversion operation, an analog signal output from a DA converter circuit is directly converted by an AD converter circuit, and the analog signal is converted after amplification with an expected gain of 2n. Based on resultant data, a gain of an amplifier circuit and an offset thereof are calculated. An analog signal to be enhanced in bit precision is amplified by the amplifier circuit and converted by the AD converter circuit, the offset is subtracted from the resultant conversion, and the result is multiplied by a ratio of the expected gain to the calculated gain to cancel gain error. Based on data with gain error canceled, acquisition of bit-extended conversion result data is performed to ensure continuity between data having different degrees of bit precision.
    Type: Application
    Filed: October 21, 2011
    Publication date: March 15, 2012
    Inventors: Yoshimi ISO, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Patent number: 8077065
    Abstract: In AD conversion of a voltage under measurement, data continuity is ensured between the result of conversion after amplification by using an amplifier circuit and the result of direct conversion without using the amplifier circuit. In AD conversion operation using a DA converter circuit, an amplifier circuit, and an AD converter circuit under the direction of a control circuit, an analog signal output from the DA converter circuit is directly converted by the AD converter circuit, and also the analog signal is converted therein after amplified by the amplifier circuit with an expected gain of 2n (ā€œnā€ represents a positive integer). Based on resultant data thus obtained, a gain of the amplifier circuit and an offset thereof are calculated.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: December 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimi Iso, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Publication number: 20110166804
    Abstract: For example, to adjust an offset of a pressure sensor, there are provided an external resistor RE and an internal resistor circuit that is connected to both ends of RE and formed in a semiconductor chip such as a processor. The internal resistor circuit includes N pieces of internal resistors RI connected in series between both ends of RE, and (N+1) pieces of switches selecting one of voltages of respective nodes of the serial resistors and outputs the same as a signal. RE has a high absolute value precision of, e.g., several ten ohms to several hundred ohms, and RI has a high relative value precision of, e.g., several kilo-ohms. Therefore, an offset adjustment range is decided at a high absolute value precision mainly by RE, and with regard to the arrangement resolution, a high precision can be obtained along with the relative value precision of the RI.
    Type: Application
    Filed: March 11, 2011
    Publication date: July 7, 2011
    Inventors: Tadashi Matsushima, Masaru Sugai, Chung Wen Hung, Yuji Shimizu
  • Patent number: 7926352
    Abstract: For example, to adjust an offset of a pressure sensor, there are provided an external resistor RE and an internal resistor circuit that is connected to both ends of RE and formed in a semiconductor chip such as a processor. The internal resistor circuit includes N pieces of internal resistors RI connected in series between both ends of RE, and (N+1) pieces of switches selecting one of voltages of respective nodes of the serial resistors and outputs the same as a signal. RE has a high absolute value precision of, e.g., several ten ohms to several hundred ohms, and RI has a high relative value precision of, e.g., several kilo-ohms. Therefore, an offset adjustment range is decided at a high absolute value precision mainly by RE, and with regard to the arrangement resolution, a high precision can be obtained along with the relative value precision of the RI.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Matsushima, Masaru Sugai, Chung Wen Hung, Yuji Shimizu
  • Publication number: 20100245140
    Abstract: In AD conversion of a voltage under measurement, data continuity is ensured between the result of conversion after amplification by using an amplifier circuit and the result of direct conversion without using the amplifier circuit. In AD conversion operation using a DA converter circuit, an amplifier circuit, and an AD converter circuit under the direction of a control circuit, an analog signal output from the DA converter circuit is directly converted by the AD converter circuit, and also the analog signal is converted therein after amplified by the amplifier circuit with an expected gain of 2n (ā€œnā€ represents a positive integer). Based on resultant data thus obtained, a gain of the amplifier circuit and an offset thereof are calculated.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Inventors: Yoshimi ISO, Kakeru Kimura, Tadashi Matsushima, Yuji Shimizu
  • Publication number: 20090165564
    Abstract: For example, to adjust an offset of a pressure sensor, there are provided an external resistor RE and an internal resistor circuit that is connected to both ends of RE and formed in a semiconductor chip such as a processor. The internal resistor circuit includes N pieces of internal resistors RI connected in series between both ends of RE, and (N+1) pieces of switches selecting one of voltages of respective nodes of the serial resistors and outputs the same as a signal. RE has a high absolute value precision of, e.g., several ten ohms to several hundred ohms, and RI has a high relative value precision of, e.g., several kilo-ohms. Therefore, an offset adjustment range is decided at a high absolute value precision mainly by RE, and with regard to the arrangement resolution, a high precision can be obtained along with the relative value precision of the RI.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Inventors: Tadashi MATSUSHIMA, Masaru SUGAI, Chung Wen Hung, Yuji SHIMIZU
  • Patent number: 5323242
    Abstract: In a video signal apparatus, a carrier signal generating circuit includes a VCO for generating a signal having a frequency at least twice that of a carrier signal necessary for conversion to a lower band with a sub-carrier in an NTSC system, a one-half divider circuit for dividing the VCO frequency signal by two, a delayed flip-flop circuit for receiving the divided signal and the sub-carrier signal to generate a difference frequency signal, a 1/40 divider circuit for dividing the Q output, a phase comparator circuit for comparing the phases of the 1/40 divided signal and the horizontal synchronizing signal to output a phase difference, a frequency discriminator circuit for comparing the phase of the flip-flop output with the frequency-divided output of the horizontal synchronizing signal to output a frequency error, and a circuit for converting the output of the phase comparator circuit and the frequency error into DC voltages and applying their sum as a control voltage for the VCO.
    Type: Grant
    Filed: January 12, 1990
    Date of Patent: June 21, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering, Ltd.
    Inventors: Norihisa Yamamoto, Hirokazu Kitamura, Katsuyoshi Yamashige, Takashi Kurihara, Tadashi Matsushima
  • Patent number: 4986159
    Abstract: A digital electronic musical instrument for synthesizing a musical waveform by computing high harmonics. The musical instrument includes a musical waveform generator, an overflow detection circuit and a data selection circuit. A musical waveform is preferably added at an adder which outputs an added musical waveform. This output added musical waveform is checked to determine if an overflow condition occurs. A data selection circuit receives the added musical waveform and establishes level limited data and non level limited data. The data selection circuit selects the level limited data upon occurrence of an overflow condition and selects non level limited data when no overflow condition exists.
    Type: Grant
    Filed: December 20, 1989
    Date of Patent: January 22, 1991
    Assignee: Kabushiki Kaisha Kawaigakki Seisakusho, Shiz
    Inventors: Tadashi Matsushima, Tsutomu Saito
  • Patent number: 4901615
    Abstract: A double buffer system of a small storage capacity is employed for reducing the noise generation in musical waveforms. The operations of the buffers are utilized for performing an interpolation between waveforms and between successive sample points of each waveform, whereby the number of sample points of the waveform being read out is increased to smooth its level variation, producing a good quality musical tone as if it were obtained by quantizing the synthesized musical waveform.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: February 20, 1990
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventors: Tadashi Matsushima, Tatsunori Kondo
  • Patent number: 4811644
    Abstract: The present invention is directed to an electronic musical instrument which has a circuit for calculating a harmonic function corresponding to a fundamental wave. The electronic musical instrument is provided with a circuit for generating, as the harmonic function, an in-tune function corresponding to an in-tune harmonic, a circuit for generating a phase function which imparts an arbitrary frequency number log to the in-tune harmonic and a circuit for multiplying the in-tune function and the phase function, whereby a tone close to a natural tone of an acoustic musical instrument can be created at a relatively low cost.
    Type: Grant
    Filed: November 25, 1987
    Date of Patent: March 14, 1989
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventor: Tadashi Matsushima
  • Patent number: 4646611
    Abstract: An electronic musical instrument is provided with a temporal variation circuit of SCF parameters for temporally varying the filter characteristic of a switched capacitor filter circuit, a control circuit for digitally controlling the temporal variation circuit and a touch response circuit for detecting, by scanning, touch response data in performance, whereby temporal variations of a musical waveform signal are digitally controlled.
    Type: Grant
    Filed: December 12, 1984
    Date of Patent: March 3, 1987
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventors: Yoichi Nagashima, Tatsunori Kondo, Kiyomi Takauji, Mineo Kitamura, Tadashi Matsushima, Eiji Nagashima, Masafumi Mizoguchi
  • Patent number: 4638706
    Abstract: In an electronic musical instrument which generates a musical waveform by calculating the waveform amplitude value at each sample point through Fourier synthesis, note-range variations of the musical waveform and its timbre variations in accordance with a touch response are controlled with respect to readout addresses for reading out a set of harmonic coefficient data for the Fourier synthesis from a memory having stored therein a plurality of sets of such harmonic coefficient data, thereby changing the component ratio of a harmonic coefficient which will ultimately be used as a Fourier coefficient.
    Type: Grant
    Filed: October 26, 1984
    Date of Patent: January 27, 1987
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventors: Yoichi Nagashima, Tatsunori Kondo, Kiyomi Takauji, Mineo Kitamura, Tadashi Matsushima, Eiji Nagashima, Masafumi Mizoguchi
  • Patent number: 4638709
    Abstract: In an electronic musical instrument which generates a musical waveform by calculating the waveform amplitude value at each sample point through Fourier synthesis, temporal variations of the musical waveform and its timbre variations in accordance with a touch response are controlled with respect to readout addresses for reading out a set of harmonic coefficient data for the Fourier synthesis from a memory having stored therein a plurality of sets of such harmonic coefficient data, thereby changing the component ratio of a harmonic coefficient which will ultimately be used as a Fourier coefficient.
    Type: Grant
    Filed: October 26, 1984
    Date of Patent: January 27, 1987
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventors: Yoichi Nagashima, Tatsunori Kondo, Kiyomi Takauji, Mineo Kitamura, Tadashi Matsushima, Eiji Nagashima, Masafumi Mizoguchi
  • Patent number: 4612838
    Abstract: In an electronic musical instrument which generates a musical waveform by calculating the waveform amplitude value at each sample point through Fourier synthesis, there is provided a musical waveform generator for caculating and synthesizing a temporally varying musical waveform at a plurality of sample points, memory circuits for storing two kinds of musical waveforms obtained by the musical waveform generator one after the other and an interpolation circuit for interpolating the two musical waveforms at time intervals shorter than the time intervals used in the musical waveform generator.
    Type: Grant
    Filed: October 26, 1984
    Date of Patent: September 23, 1986
    Assignee: Kabushiki Kaisha Kawai Gakki Seisakusho
    Inventors: Yoichi Nagashima, Tatsunori Kondo, Kiyomi Takauji, Mineo Kitamura, Tadashi Matsushima, Eiji Nagashima, Masafumi Mizoguchi