Patents by Inventor Tadashi Munakata

Tadashi Munakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9805980
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20160133521
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 12, 2016
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamagushi, Noriyuki Takahashi
  • Publication number: 20150004755
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 8877613
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 4, 2014
    Assignees: Renesas Electronics Corporation, Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 8083048
    Abstract: A footstep guide rail (3) (rail body 3a) is arranged so that a level H of a horizontal surface is set at the position obtained by adding a designated offset ? to a tangential line L of a drive sprocket (9) and the footstep guide rail (3) is provided, at its one end on an introductory side of the drive sprocket (9), with a curved part (13). At a reference position closest to the drive sprocket (9), the horizontal surface of the footstep guide rail (3) is changed to the curved part (13). Consequently, it is possible to absorb velocity unevenness of one footstep roller approaching the drive sprocket (9).
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: December 27, 2011
    Assignee: Toshiba Elevator Kabushiki Kaisha
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hitoshi Kawamoto, Kenichi Fujii, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Publication number: 20110020984
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: September 30, 2010
    Publication date: January 27, 2011
    Inventors: Tadashi MUNAKATA, Shingo OOSAKA, Mitsuru KINOSHITA, Yoshihiko YAMAGUCHI, Noriyuki TAKAHASHI
  • Patent number: 7816185
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: October 19, 2010
    Assignees: Renesas Electronics Corporation, Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20090291529
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: August 3, 2009
    Publication date: November 26, 2009
    Inventors: TADASHI MUNAKATA, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 7579216
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: August 25, 2009
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20080286902
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: May 12, 2008
    Publication date: November 20, 2008
    Inventors: Tadashi MUNAKATA, Shingo OOSAKA, Mitsuru KINOSHITA, Yoshihiko YAMAGUCHI, Noriyuki TAKAHASHI
  • Patent number: 7401691
    Abstract: A mountainous or valley-shaped curved part 13 is provided in a part of a footstep guide rail 3 for guiding a movement of footstep rollers 5 linked by a footstep chain 7, the part being positioned in the vicinity of a drive sprocket 9. Consequently, owing to meshing of the footstep rollers 5 with the drive sprocket 9, an unevenness in velocity of the footstep rollers 5 is absorbed by the curved part 13, so that a moving velocity of the footstep rollers 5 moving on the downstream of the curved part 13 is maintained constantly, suppressing vibrating of the footsteps 4.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: July 22, 2008
    Assignee: Toshiba Elevator Kabushiki Kaisha
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hitoshi Kawamoto, Kenichi Fujii, Tomohiko Matsuura, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Patent number: 7384820
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20070235284
    Abstract: A footstep guide rail (3) (rail body 3a) is arranged so that a level H of a horizontal surface is set at the position obtained by adding a designated offset 6 to a tangential line L of a drive sprocket (9) and the footstep guide rail (3) is provided, at its one end on an introductory side of the drive sprocket (9), with a curved part (13). At a reference position closest to the drive sprocket (9), the horizontal surface of the footstep guide rail (3) is changed to the curved part (13). Consequently, it is possible to absorb velocity unevenness of one footstep roller approaching the drive sprocket (9).
    Type: Application
    Filed: December 1, 2006
    Publication date: October 11, 2007
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hitoshi Kawamoto, Kenichi Fujii, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Publication number: 20070235285
    Abstract: A footstep guide rail (3) (rail body 3a) is arranged so that a level H of a horizontal surface is set at the position obtained by adding a designated offset ? to a tangential line L of a drive sprocket (9) and the footstep guide rail (3) is provided, at its one end on an introductory side of the drive sprocket (9), with a curved part (13). At a reference position closest to the drive sprocket (9), the horizontal surface of the footstep guide rail (3) is changed to the curved part (13). Consequently, it is possible to absorb velocity unevenness of one footstep roller approaching the drive sprocket (9).
    Type: Application
    Filed: April 12, 2006
    Publication date: October 11, 2007
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hitoshi Kawamoto, Kenichi Fujii, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Publication number: 20070007106
    Abstract: A mountainous or valley-shaped curved part 13 is provided in a part of a footstep guide rail 3 for guiding a movement of footstep rollers 5 linked by a footstep chain 7, the part being positioned in the vicinity of a drive sprocket 9. Consequently, owing to meshing of the footstep rollers 5 with the drive sprocket 9, an unevenness in velocity of the footstep rollers 5 is absorbed by the curved part 13, so that a moving velocity of the footstep rollers 5 moving on the downstream of the curved part 13 is maintained constantly, suppressing vibrating of the footsteps 4.
    Type: Application
    Filed: February 28, 2003
    Publication date: January 11, 2007
    Applicant: TOSHIBA ELEVATOR KABUSHIKI KAISHA
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hiroshi Kawamoto, Kenichi Fujii, Tomohiko Matsuura, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Publication number: 20060141677
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: February 24, 2006
    Publication date: June 29, 2006
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20060108196
    Abstract: A mountainous or valley-shaped curved part 13 is provided in a part of a footstep guide rail 3 for guiding a movement of footstep rollers 5 linked by a footstep chain 7, the part being positioned in the vicinity of a drive sprocket 9. Consequently, owing to meshing of the footstep rollers 5 with the drive sprocket 9, an unevenness in velocity of the footstep rollers 5 is absorbed by the curved part 13, so that a moving velocity of the footstep rollers 5 moving on the downstream of the curved part 13 is maintained constantly, suppressing vibrating of the footsteps 4.
    Type: Application
    Filed: September 12, 2005
    Publication date: May 25, 2006
    Applicant: Toshiba Elevator Kabushiki Kaisha
    Inventors: Yoshinobu Ishikawa, Tadashi Munakata, Yoshio Ogimura, Nobuhiko Teshima, Shigeo Nakagaki, Hitoshi Kawamoto, Kenichi Fujii, Tomohiko Matsuura, Yoshifumi Ikeda, Kazuhisa Hara, Takayuki Kikuchi
  • Patent number: 7033857
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: April 25, 2006
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Publication number: 20040038510
    Abstract: A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon, fixing plural semiconductor chips to the plural device areas respectively, then sealing the plural semiconductor chips all together with resin to form a block sealing member, dividing the block sealing member and the matrix substrate for each of the device areas by dicing, thereafter rubbing a surface of each of the diced sealing member portions with a brush, then storing semiconductor devices formed by the dicing once into pockets respectively of a tray, and conveying the semiconductor devices each individually from the tray. Since the substrate dividing work after block molding is performed by dicing while vacuum-chucking the surface of the block sealing member, the substrate division can be done without imposing any stress on an external terminal mounting surface of the matrix substrate.
    Type: Application
    Filed: June 17, 2003
    Publication date: February 26, 2004
    Applicants: Hitachi, Ltd., Renesas Northern Japan Semiconductor, Inc.
    Inventors: Tadashi Munakata, Shingo Oosaka, Mitsuru Kinoshita, Yoshihiko Yamaguchi, Noriyuki Takahashi
  • Patent number: 6491136
    Abstract: An elevator apparatus is provided with an elevator path having a restricted height. Under a roping ratio of 1:1, a thin driving unit having a traction sheave 1 and a driving mechanism 2 is positioned between an inner wall 3a of the elevator path 3 and a space occupied by an elevator car 4 rising and falling in the elevator path 3. One end of a suspension rope 7 is fixed to the elevator car 4 in a position below a ceiling 4c of the elevator car 4. With the arrangement, the car 4 can move close to the ceiling 4c of the elevator car 4 effectively. Further, it is possible to reduce respective heights of the elevator path 3 and a building equipped with the elevator apparatus.
    Type: Grant
    Filed: March 26, 2001
    Date of Patent: December 10, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyoshi Kobayashi, Tadashi Munakata, Kosei Kamimura, Yasuyuki Wagatsuma, Hisao Yamamoto, Koji Yajima