Patents by Inventor Tadashi Muto

Tadashi Muto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5917752
    Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: June 29, 1999
    Assignees: Hitachi, Ltd., Hitachi VSLI Engineering Corp.
    Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
  • Patent number: 5844842
    Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: December 1, 1998
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
  • Patent number: 5781476
    Abstract: Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: July 14, 1998
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.
    Inventors: Koichi Seki, Takeshi Wada, Tadashi Muto, Kazuyoshi Shoji, Yasurou Kubota, Hitoshi Kume
  • Patent number: 5345515
    Abstract: A method of inspecting cleanliness of top sliber. The method classifies detected defects into pillwise defects and vegetal defects by introducing roundness, slenderness, gradation, dispersion, area, shape, gradation ratio, and length discernment against image signals of inspected top slibers picked up by an image sensor. An apparatus for inspecting cleanliness of top sliders is utilized. The apparatus initially picks up an image of uniformly spread top slibers conveyed to the apparatus and then processes the image signal with an image processing unit provided therefor. The method involves classifying defects on the top sliber into pillwise defects and vegetal defects in the top sliber based on the generated image signal.
    Type: Grant
    Filed: March 18, 1992
    Date of Patent: September 6, 1994
    Assignee: Kanebo Ltd.
    Inventors: Noriyuki Nishi, Tadashi Muto, Shinichi Takayama
  • Patent number: 5315547
    Abstract: In a nonvolatile semiconductor memory device, a high voltage is selectively exerted between a word line to which the control gates of nonvolatile semiconductor memory elements are coupled and a source line to which the sources of the nonvolatile semiconductor memory elements are coupled, whereby charges stored in the floating gates are extracted through the source line. In addition, the nonvolatile semiconductor memory elements to be erased are provided with a source potential having ramp-rate characteristics such that the sources are gradually raised from a low voltage to the high voltage. Thus, the erasure of a predetermined part of the memory array of the memory device becomes possible in accordance with the division of the source lines or that of the word lines, and an excessive intense electric field can be prevented from acting between the floating gates and the sources because a ramp rate is used for the erasing high voltage.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: May 24, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kazuyoshi Shoji, Tadashi Muto, Yasurou Kubota, Koichi Seki, Kazuto Izawa, Shinji Nabetani, deceased
  • Patent number: 5097446
    Abstract: A time circuit is provided for a nonvolatile memory device which can electrically be written into. When the write operation on a particular memory cell lasting a relatively long period of time is specified from an external device, the memory device stops the write operation on that memory cell, irrespective of the external write operaiton specification, when the time set on the timer circuit has elapsed. The nonvolatile memory device has memory cells, each consisting of a single transistor. The erase operation on the memory cells is controlled according to a current flowing through these memory cells.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: March 17, 1992
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kazuyoshi Shoji, Takaaki Hagiwara, Tadashi Muto, Shun-ichi Saeki, Yasurou Kubota, Kazuto Izawa, Yoshiaki Kamigaki, Shin-ichi Minami, Yuko Nabetani
  • Patent number: 4996571
    Abstract: The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: February 26, 1991
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hitoshi Kume, Yoshiaki Kamigaki, Tetsuo Adachi, Toshihisa Tsukada, Kazuhiro Komori, Toshiaki Nishimoto, Tadashi Muto, Toshiko Koizumi
  • Patent number: 4972371
    Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: November 20, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Komori, Takaaki Hagiwara, Satoshi Meguro, Toshiaki Nishimoto, Takeshi Wada, Kiyofumi Uchibori, Tadashi Muto, Hitoshi Kume, Hideaki Yamamoto, Tetsuo Adachi, Toshihisa Tsukada, Toshiko Koizumi