Abstract: According to the present invention, the compiler inputs a plurality of pieces of source data composing a large-scale program on basis of an user-designated information, subjects the source data to syntax analysis, and analyzes attributes of a relation between caller (parent procedure) and callee (child procedure) in the source data from the result of the syntax analysis and registers the attribute in a data table. Then, if the the callee is not registered in the data table, the compiler marks the attributes of the caller procedure with “optimization unnecessary” and then optimizes other procedures excluding the parent procedure marked with “optimization unnecessary”.

Abstract: A compiling processing apparatus which compiles a program operating in a computer having a cache memory. This apparatus collects memory access data for the cache memory, analyzes confliction relationships between them, determines whether or not an instruction for confliction memory access data relocates, relocates the instruction if relocation is possible, and reduces the number of cache miss. Further, this apparatus recognizes memory access data in a continuous area, audits recognized memory access data alignment, generates an instruction of pair-load/pair-store, and reduces the number of memory accesses.

Abstract: The entire space of a loop is analyzed for dependencies between target array elements so that dependency ID's are assigned to the target array elements. Optimization is carried out on the basis of the dependency ID's. Dependency ID's covering dependency for an arbitrary turn of the loop are reassigned to the target array elements that have been subjected to optimization, whereupon a further optimization is carried out. An examination for identifying overlappings is carried out on the basis of the dependency ID assigned to the target array elements so that instruction scheduling is carried out.

Abstract: An object of the present invention is to realize a compiling apparatus producing an object program which can be executed at a high speed. In a compiling apparatus according to the present invention, an aliasing address comparison instruction generating unit inserts a instruction to compare the two memory addresses of each pair of data expressions whose overlap is judged to be obscure, generates a plurality of paths defined by combinations of conditions whether or not memory addresses of data expressions of each pair overlap, and generates a instruction to branch to one of the paths according to a comparison result obtained by the instruction in an execution of a compiled program, and an optimization unit for respectively optimizing the paths. When the object program is executed, one path corresponding to a practical condition is selected from the plurality of paths, and only the selected path is executed.