Patents by Inventor Tadashi Nakasugi

Tadashi Nakasugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11408092
    Abstract: A method for heat-treating a silicon single crystal wafer to control a BMD density thereof to achieve a predetermined BMD density by performing an RTA heat treatment on a silicon single crystal wafer composed of an Nv region in a nitriding atmosphere, and then performing a second heat treatment, the method including: formulating a relational equation for a relation between BMD density and RTA temperature in advance; and determining an RTA temperature for achieving the predetermined BMD density according to the relational equation. Consequently, a method for heat-treating a silicon single crystal wafer for manufacturing an annealed wafer or an epitaxial wafer each having defect-free surface and a predetermined BMD density in a bulk portion thereof.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: August 9, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Wei Feng Qu, Ken Sunakawa, Tadashi Nakasugi
  • Publication number: 20210062366
    Abstract: A method for heat-treating a silicon single crystal wafer to control a BMD density thereof to achieve a predetermined BMD density by performing an RTA heat treatment on a silicon single crystal wafer composed of an Nv region in a nitriding atmosphere, and then performing a second heat treatment, the method including: formulating a relational equation for a relation between BMD density and RTA temperature in advance; and determining an RTA temperature for achieving the predetermined BMD density according to the relational equation. Consequently, a method for heat-treating a silicon single crystal wafer for manufacturing an annealed wafer or an epitaxial wafer each having defect-free surface and a predetermined BMD density in a bulk portion thereof.
    Type: Application
    Filed: December 25, 2018
    Publication date: March 4, 2021
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Wei Feng QU, Ken SUNAKAWA, Tadashi NAKASUGI
  • Patent number: 10886129
    Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 5, 2021
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi Ohtsuki, Tadashi Nakasugi, Hiroshi Takeno, Katsuyoshi Suzuki
  • Publication number: 20190267239
    Abstract: A method for manufacturing a semiconductor device, including forming a Fin structure on a semiconductor silicon substrate, performing ion implantation into the Fin structure, and subsequently performing recovery heat treatment on the semiconductor silicon substrate to recrystallize silicon of the Fin structure, wherein the Fin structure is processed so as not to have an end face of a {111} plane of the semiconductor silicon onto a sidewall of the Fin structure to be formed. It also includes a method for manufacturing a semiconductor device that is capable of preventing a defect from being introduced into a Fin structure when the Fin structure is subjected to ion implantation and recovery heat treatment.
    Type: Application
    Filed: July 3, 2017
    Publication date: August 29, 2019
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Tsuyoshi OHTSUKI, Tadashi NAKASUGI, Hiroshi TAKENO, Katsuyoshi SUZUKI
  • Publication number: 20050079690
    Abstract: When manufacturing a silicon epitaxial wafer by forming a silicon epitaxial layer through vapor phase growth on a front surface of a semiconductor substrate W with a CVD oxide film formed on a rear surface thereof, there is used a susceptor (20) where a pocket (21) inside which the semiconductor substrate W is disposed is formed and at least one pore (22) which passes through the susceptor (20) to a rear surface thereof and is open even during the vapor phase growth is formed in a more central position than that of an outermost peripheral portion inside the pocket (21), and the semiconductor substrate W is disposed such that the CVD oxide film faces the at least one pore (22), thus forming the silicon epitaxial layer on the front surface of the semiconductor substrate W through the vapor phase growth.
    Type: Application
    Filed: November 11, 2003
    Publication date: April 14, 2005
    Inventors: Akihiko Suka, Tadashi Nakasugi, Takeshi Arai