Patents by Inventor Tadashi Nitta

Tadashi Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140056094
    Abstract: In a state where a signal (IN) is at “H” and an NMOS transistor (403) is on, when a signal (PCLK) changes to “H” and a PMOS transistor (401) turns off, an output node (N1) becomes coupled to a word-line activation signal (WACTCLK) via the NMOS transistor (403). When the word-line activation signal (WACTCLK) changes to “L,” a word line signal (MWL) changes to “L.” Since the signal (PCLK) is at “H” and the NMOS transistor (405) is on, this NMOS transistor (405) can assist discharging of the word-line activation signal (WACTCLK) to a ground voltage.
    Type: Application
    Filed: July 19, 2013
    Publication date: February 27, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Tadashi NITTA, Tsuyoshi KOIKE
  • Publication number: 20120002485
    Abstract: In a semiconductor memory circuit, a write voltage generation circuit receives an output voltage of a voltage boosting circuit to generate a write voltage to a memory cell. When the write voltage is low, a number-of-bits adjustment circuit increases the number of write bits of memory cells before write operation is performed. On the other hand, when the write voltage to a memory cell is high, the number-of-bits adjustment circuit decreases the number of write bits of memory cells before write operation is performed. The area and write time of the voltage boosting circuit can be reduced while the current supply capability of the voltage boosting circuit is efficiently used.
    Type: Application
    Filed: September 15, 2011
    Publication date: January 5, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Hitoshi Suwa, Takafumi Maruyama, Takashi Ono, Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
  • Patent number: 7808846
    Abstract: A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to thereby generate a plurality of delayed clocks; a plurality of delayed input signal holding circuits for holding the delayed input signal on the plurality of delayed clocks, respectively; an input signal latch timing determination circuit for outputting a determination signal indicating a timing at which to latch the delayed input signal, based on a plurality of held signals held by the delayed input signal holding circuits; and a held signal selector circuit for integrating the plurality of held signals into a single signal.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventor: Tadashi Nitta
  • Patent number: 7782707
    Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 24, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuyo Nishikawa, Masahiro Ueminami, Tadashi Nitta
  • Patent number: 7751222
    Abstract: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. A gate of the first selecting transistor is connected to the 2·N?1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: July 6, 2010
    Assignee: Panasonic Corporation
    Inventor: Tadashi Nitta
  • Publication number: 20100031001
    Abstract: In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller.
    Type: Application
    Filed: June 18, 2009
    Publication date: February 4, 2010
    Inventors: Masahiro Ueminami, Kazuyo Nishikawa, Masahiro Kuramochi, Tadashi Nitta, Toshiki Mori
  • Patent number: 7522465
    Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
  • Publication number: 20090080231
    Abstract: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. A gate of the first selecting transistor is connected to the 2·N?1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.
    Type: Application
    Filed: November 10, 2008
    Publication date: March 26, 2009
    Applicant: PANASONIC CORPORATION
    Inventor: Tadashi NITTA
  • Publication number: 20090080269
    Abstract: A semiconductor memory device comprises an address terminal through which an address for reading out stored data in a memory array is input, a clock input terminal through which an input clock is input, a data output terminal through which data read out from the memory array in accordance with the address is output, and a clock output terminal through which an output clock synchronous with the input clock is output. The clock output terminal invariably outputs one of a first voltage and a second voltage. Only when valid data is output from the data output terminal, the clock output terminal causes an output voltage to go from the first voltage to the second voltage or from one voltage to the other voltage.
    Type: Application
    Filed: March 30, 2007
    Publication date: March 26, 2009
    Inventors: Kazuyo Nishikawa, Masahiro Ueminami, Tadashi Nitta
  • Publication number: 20090040848
    Abstract: A semiconductor memory device to/from which a data signal is input/output in synchronism with a clock, including: an input signal delaying circuit for delaying an input signal to output the delayed input signal; a delayed clock generation circuit for delaying an input clock by different amounts of delay time to thereby generate a plurality of delayed clocks; a plurality of delayed input signal holding circuits for holding the delayed input signal on the plurality of delayed clocks, respectively; an input signal latch timing determination circuit for outputting a determination signal indicating a timing at which to latch the delayed input signal, based on a plurality of held signals held by the delayed input signal holding circuits; and a held signal selector circuit for integrating the plurality of held signals into a single signal.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 12, 2009
    Inventor: Tadashi NITTA
  • Patent number: 7457142
    Abstract: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. Agate of the first selecting transistor is connected to the 2·N?1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: November 25, 2008
    Assignee: Panasonic Corporation
    Inventor: Tadashi Nitta
  • Publication number: 20070274148
    Abstract: A semiconductor memory device includes: a power supply circuit for outputting a power supply voltage used for reading out data; and a power supply circuit status determination circuit for determining whether an operation status of the power supply circuit is such that data can be read out normally. The output of readout data is suppressed while it is determined by the power supply circuit status determination circuit that the operation status is such that data cannot be read out normally.
    Type: Application
    Filed: March 1, 2007
    Publication date: November 29, 2007
    Inventors: Tadashi Nitta, Kazuyo Nishikawa, Masahiro Ueminami
  • Publication number: 20070139992
    Abstract: A basic cell comprises a memory cell capable of retaining data having at least a binary value, a first selecting transistor connected between a first terminal of the memory cell and the Mth bit line, and a second selecting transistor connected between the first terminal of the memory cell and the M+1th bit line. Agate of the first selecting transistor is connected to the 2·N?1th selecting line, and a gate of the second selecting transistor is connected to the 2·Nth selecting line.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Inventor: Tadashi Nitta