Patents by Inventor Tadashi Oda

Tadashi Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150159801
    Abstract: Provided is an electrically driven support base which is configured so as to prevent the rotation-induced shaking of a pole for supporting a camera mounting head and so as to enable the automatic adjustment of the position in height of a camera. One end of a flexible transmission belt (drive cord (12)) is connected to a multi-stage telescoping pole (2) having a mounting head (50) provided to the front end pole (46) of the multi-stage telescoping pole (2), and the drive cord (12) is engaged with a gear connected to an electric motor (23). The multi-stage telescoping pole (2) is extended or retracted by paying out or pulling in the drive cord (12). A camera means can be mounted on the mounting head (50), and the multi-stage telescoping pole (2) is provided with a rotation-induced shaking prevention means for each stage pole.
    Type: Application
    Filed: June 6, 2013
    Publication date: June 11, 2015
    Inventor: Tadashi Oda
  • Patent number: 7317640
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: January 8, 2008
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yuki Matsuda, Tadashi Oda
  • Publication number: 20060279995
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Application
    Filed: August 15, 2006
    Publication date: December 14, 2006
    Inventors: Yuki Matsuda, Tadashi Oda
  • Patent number: 7130218
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: October 31, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yuki Matsuda, Tadashi Oda
  • Publication number: 20050157556
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Application
    Filed: January 25, 2005
    Publication date: July 21, 2005
    Inventors: Yuki Matsuda, Tadashi Oda
  • Patent number: 6853582
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: February 8, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yuki Matsuda, Tadashi Oda
  • Patent number: 6791884
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 14, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yuki Matsuda, Tadashi Oda
  • Patent number: 6725449
    Abstract: A semiconductor test program debugging apparatus is disclosed to which data concerning a packet input to and output from the packet transfer memory device is supplied, and which extracts a part corresponding to the packet from data input to and output from the memory device with response to a test signal generated by a tester simulator and displays the details of the part.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: April 20, 2004
    Assignee: Advantest Corporation
    Inventors: Yoshinori Maeda, Hironori Maeda, Tadashi Oda
  • Publication number: 20030090947
    Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.
    Type: Application
    Filed: December 23, 2002
    Publication date: May 15, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuki Matsuda, Tadashi Oda