Abstract: Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position.

Abstract: Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position.

Abstract: There is provided a technique that includes a first controller configured to acquire event data generated at a time of transferring a substrate and alarm data generated at a time of occurrence of a transfer error, a recorder configured to, while recording a transfer operation of the substrate as first image data, record the transfer operation of the substrate as second image data having a higher resolution than the first image data, a second controller configured to store the first image data in a first memory based on the event data, and store the second image data in a second memory based on the alarm data, and an operating controller configured to display at least the first image data and the second image data. The second controller displays both the first image data and the second image data on a same screen.

Abstract: There is provided a configuration that includes a substrate holder configured to hold substrates; a transfer mechanism configured to transfer the substrates to the substrate holder; and a controller configured to: acquire a number of substrates mountable on the substrate holder and a number of the product substrates to be mounted on the substrate holder; divide the product substrates into product substrate groups; divide the dummy substrates into dummy substrate groups based on the number of the product substrates, the number of the substrates mountable on the substrate holder, and a number of the product substrate groups; combine the product substrate groups and the dummy substrate groups; create substrate arrangement data for distributing and mounting the product substrates on the substrate holder; and cause the transfer mechanism to transfer the substrates according to the substrate arrangement data.

Abstract: Described herein is a technique capable of detecting a substrate state without contacting the substrate. According to one aspect of the technique, there is provided (a) loading a substrate retainer, where a plurality of substrates is placed, into a reaction tube; (b) processing the plurality of the substrates by supplying a gas into the reaction tube; (c) unloading the substrate retainer out of the reaction tube after the plurality of the substrates is processed; and (d) detecting the plurality of the substrates placed on the substrate retainer after the substrate retainer is rotated by a first angle with respect to a transferable position, wherein the plurality of the substrates is transferable to/from the substrate retainer in the transferable position.

Abstract: There is provided a technique that includes a first controller configured to acquire event data generated at a time of transferring a substrate and alarm data generated at a time of occurrence of a transfer error, a recorder configured to, while recording a transfer operation of the substrate as first image data, record the transfer operation of the substrate as second image data having a higher resolution than the first image data, a second controller configured to store the first image data in a first memory based on the event data, and store the second image data in a second memory based on the alarm data, and an operating controller configured to display at least the first image data and the second image data. The second controller displays both the first image data and the second image data on a same screen.

Abstract: This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular memory block after a failure is detected in the block. The test system which tests writing and erasing as a unit of block in the memory under test. The test system includes a register provided for each memory under test for holding a first failure generated in a particular block at a first control signal from a pattern generator, establishes a pass result for the particular block for test cycles after the first failure, thereby treating any failure result for the particular block as the pass result thereafter; and resets the register at a cycle specified by a second control signal from the pattern generator to release the pass result.

Abstract: This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular block after a failure is detected in the block. In the test system which tests writing and erasing as a unit of block in the memory under test by using a match function includes a register (61) provided for each memory under test (MUTn) for holding a first failure generated in a particular block at a first control signal (Ca) from a pattern generator (2), establishes a match condition, a pass condition, and a write inhibit condition for the particular block for test cycles after the first failure; and resets the register at a cycle specified by a second control signal (Cb) from the pattern generator to release the match condition, pass condition, and write inhibit condition.

Abstract: In an address generating device wherein addresses are generated by an address computation part in response to data and control signals read out of an instruction memory and are provided to a memory under test, a command control bit for storing a command control signal is provided in the instruction memory and a command register is provided for storing a command read out of a data area of the instruction memory. The output from the address computation part and the output from the command register are input into a first multiplexer, which selects either one of the two inputs in response to a command control signal read out of the command control bit. The output from the first multiplexer is applied to a descrambler, wherein it is translated to a physical address. A second multiplexer is provided for selecting either one of the outputs from the descrambler and the first multiplexer in such an instance.

Abstract: A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate. When they match, a compared result that represents pass is output. When they mismatch, a compared result that represents fail is output. A match signal WC detected by the XOR gate is held in a register. The register outputs an inhibition signal to an inhibition gate of the test memory. Thus, a write enable signal WE is inhibited from being supplied to the test memory. In addition, the inhibition signal is supplied to a compared result inhibition gate. The compared result inhibition gate causes the compared result to be passed and prevents the test memory from being excessively written.

Abstract: A clutch driven plate comprising a clutch facing plate molded from a clutch facing material comprising a fiber, a binder, and a friction modifier and a back-up plate carrying the clutch facing plate, wherein a number of dimples are formed on the surface of the clutch facing plate. The clutch driven plate is obtainable by thermo-compression molding a back-up plate and a clutch facing material comprising a fiber, a binder, and a friction modifier to integrate the plate and clutch facing material into one body.

Abstract: A clutch driven plate comprising a clutch facing plate molded from a clutch facing material comprising a fiber, a binder, and a friction modifier and a back-up plate carrying the clutch facing plate, wherein a number of dimples are formed on the surface of the clutch facing plate.The clutch driven plate is obtainable by thermo-compression molding a back-up plate and a clutch facing material comprising a fiber, a binder, and a friction modifier to integrate them in one body.