Patents by Inventor Tadashi Omae
Tadashi Omae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8325524Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: GrantFiled: October 13, 2010Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
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Publication number: 20110024814Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Inventors: Yasushi OKA, Tadashi Omae, Takesada Akiba
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Patent number: 7839683Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: GrantFiled: September 18, 2008Date of Patent: November 23, 2010Assignee: Renesas Electronics CorporationInventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
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Publication number: 20090080257Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: ApplicationFiled: September 18, 2008Publication date: March 26, 2009Inventors: YASUSHI OKA, Tadashi Omae, Takesada Akiba
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Patent number: 6660586Abstract: A process for manufacturing a semiconductor device includes the following steps applied to a semiconductor substrate having, on its main surface, a plurality of separation oxide films, formed in stripes parallel to each other, and gate oxide films formed in the regions placed between separation oxide films, wherein pieces of a polysilicon layer are formed so as to extend from areas above gate oxide films to areas above portions of separation oxide films on both sides of the gate oxide films and wherein a first resist is formed so as to cover the top surfaces of polysilicon layer: the injection step of injecting an impurity into polysilicon layer above separation oxide films; and the thermal diffusion step of carrying out a heat processing so that the injected impurity diffuses to the regions above gate oxide films within polysilicon layer.Type: GrantFiled: March 13, 2002Date of Patent: December 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Ippei Shimizu, Satoshi Shimizu, Tadashi Omae
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Publication number: 20030013226Abstract: A process for manufacturing a semiconductor device includes the following steps applied to a semiconductor substrate having, on its main surface, a plurality of separation oxide films, formed in stripes parallel to each other, and gate oxide films formed in the regions placed between separation oxide films, wherein pieces of a polysilicon layer are formed so as to extend from areas above gate oxide films to areas above portions of separation oxide films on both sides of the gate oxide films and wherein a first resist is formed so as to cover the top surfaces of polysilicon layer: the injection step of injecting an impurity into polysilicon layer above separation oxide films; and the thermal diffusion step of carrying out a heat processing so that the injected impurity diffuses to the regions above gate oxide films within polysilicon layer.Type: ApplicationFiled: March 13, 2002Publication date: January 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Ippei Shimizu, Satoshi Shimizu, Tadashi Omae
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Patent number: 6414393Abstract: The invention provides a semiconductor device having a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which a connection wiring is formed on each layer, wherein a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring, the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.Type: GrantFiled: December 20, 2000Date of Patent: July 2, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Jun Sumino, Tadashi Omae, Satoshi Shimizu
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Publication number: 20010052649Abstract: The invention provides a semiconductor device having a multilayer wiring structure in which a plurality of layers are provided on a substrate and in which a connection wiring is formed on each layer, wherein a dummy pattern almost as high as the connection wiring is provided in a predetermined region of each layer so that an outer peripheral portion of the dummy pattern is adjacent to the connection wiring, the dummy pattern is formed linearly at least on the outer peripheral portion, and a distance between a linearly formed portion and a portion inside of the linearly formed portion is set to be equal to or narrower than a distance between the connection wiring and the linearly formed portion.Type: ApplicationFiled: December 20, 2000Publication date: December 20, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Jun Sumino, Tadashi Omae, Satoshi Shimizu
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Patent number: 5847995Abstract: The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.Type: GrantFiled: May 7, 1997Date of Patent: December 8, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shinichi Kobayashi, Shinji Kawai, Tadashi Omae, Makoto Oi, Akinori Matsuo, Masashi Wada, Kenji Kozakai