Patents by Inventor Tadashi Sakaue

Tadashi Sakaue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8066597
    Abstract: A derailleur comprises a base member, a movable member; a linkage mechanism including a link member coupled to the base member and to the movable member so that the movable member moves relative to the base member, a motor including a drive member, and a driven member driven by the drive member. The driven member is coupled to the link member so that the link member moves relative to the base member to move the movable member relative to the base member. A clutch is disposed in a power transmission path between the motor and the link member.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: November 29, 2011
    Assignee: Shimano, Inc.
    Inventor: Tadashi Sakaue
  • Publication number: 20080227572
    Abstract: A derailleur comprises a base member, a movable member; a linkage mechanism including a link member coupled to the base member and to the movable member so that the movable member moves relative to the base member, a motor including a drive member, and a driven member driven by the drive member. The driven member is coupled to the link member so that the link member moves relative to the base member to move the movable member relative to the base member. A clutch is disposed in a power transmission path between the motor and the link member.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Applicant: SHIMANO, INC.
    Inventor: TADASHI SAKAUE
  • Patent number: 5051806
    Abstract: A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively close to the gate signal input area.
    Type: Grant
    Filed: July 27, 1989
    Date of Patent: September 24, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Toshihide Ujihara, Shuroku Sakurada, Tadashi Sakaue, Shuji Musha
  • Patent number: 5003369
    Abstract: A thyristor of the overvoltage self-protection type capable of performing a turn-on operation certainly without being damaged even when an overvoltage is applied across the thyristor is disclosed in which a P-base layer is provided with a recess having such a depth as to generate an avalanche in the vicinity of the bottom of the recess when the overvoltage is applied across the thyristor, and a portion of a P.sup.+ -layer formed on the surface of the recess is kept in contact with an N-emitter layer.
    Type: Grant
    Filed: April 14, 1988
    Date of Patent: March 26, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Kanda, Katsumi Akabane, Tadashi Sakaue
  • Patent number: 4868625
    Abstract: A gate turn-off (GTO) thyristor has a plurality of unit GTO thyristors of strip-like configuration in a same semiconductor substrate, each unit GTO thyristor being constructed of an N emitter layer, P base layer, N base layer and P emitter layer. The P base and N base layers are shared in common for all the unit GTO thyristors which are formed in a multi-ring configuration. The exposed area of the P emitter layer of a unit GTO thyristor located far from the gate signal input area is made smaller than that of the P emitter layer of a unit GTO thyristor located relatively closer to the gate signal input area.
    Type: Grant
    Filed: July 8, 1987
    Date of Patent: September 19, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toshihide Ujihara, Shuroku Sakurada, Tadashi Sakaue, Shuji Musha
  • Patent number: 4775916
    Abstract: A pressure contact semiconductor device has a semiconductor substrate disposed on a metal post electrode through metal electrode plate, an insulating ring engaged with the periphery of the metal post electrode extends to the periphery of the metal electrode plate and is brought into contact therewith at a certain height with a sufficient contact pressure. The semiconductor substrate is positioned precisely with respect to the metal post electrode so that a gate electrode ring is precisely positioned on a gate electrode film formed on the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: August 21, 1986
    Date of Patent: October 4, 1988
    Assignees: Hitachi Ltd., Hitachi Haramachi Semi-Conductor Ltd.
    Inventors: Shigeyasu Kouzuchi, Shuroku Sakurada, Tadashi Sakaue, Masafumi Ono
  • Patent number: 4653329
    Abstract: A circular diaphragm with an annular thin portion has a smooth front surface, and coaxial but spaced inner and outer cylinders are secured to a rear surface of the diaphragm across said annular thin portion. Opposite edges of a rectangular strain member which is operatively connected to the disphragm through the inner cylinder are secured to a free end of the outer cylinder.
    Type: Grant
    Filed: September 30, 1985
    Date of Patent: March 31, 1987
    Assignee: Ohkura Electric Co., Ltd.
    Inventors: Tatsuo Sagara, Tadashi Sakaue
  • Patent number: 4305088
    Abstract: A semiconductor device comprises a heat-radiating electrode plate, a semiconductor element soldered to the depressed portion formed in the heat-radiating electrode plate, a header lead soldered onto the semiconductor element, a terminal board of insulating material fixed on the heat-radiating electrode plate, and a lead terminal secured to the terminal board and with the one end thereof electrically and mechanically connected to the header lead. The semiconductor device further comprises means for mitigating the transmission to the solder of the stress generated along the length of the header lead by the difference in the coefficient of thermal expansion among the component parts, and means for alleviating the lateral stress generated in the solder by the difference in the coefficient of thermal expansion between the header lead and the semiconductor element.
    Type: Grant
    Filed: October 10, 1980
    Date of Patent: December 8, 1981
    Assignees: Hitachi, Ltd., Hitachi Haramachi Semi-Conductor, Ltd.
    Inventors: Kazutoyo Narita, Tadashi Sakaue, Noboru Kawasaki, Motoji Nakajima
  • Patent number: 4057825
    Abstract: A semiconductor device has a composite metal heat-radiating plate consisting of, for example, two copper layers for serving as a thermally and electrically conducting medium and an iron layer for giving mechanical strength, interposed between the copper layers, in which the semiconductor element is directly or indirectly, electrically and mechanically coupled by soldering to one of the copper layers.
    Type: Grant
    Filed: July 1, 1976
    Date of Patent: November 8, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Kazutoyo Narita, Tadashi Sakaue, Yuzi Niino