Patents by Inventor Tadashi Someya

Tadashi Someya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230056494
    Abstract: A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.
    Type: Application
    Filed: March 15, 2022
    Publication date: February 23, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Wataru MORIYAMA, Hayato KONNO, Takao NAKAJIMA, Fumihiro KONO, Masaki FUJIU, Kiyoaki IWASA, Tadashi SOMEYA
  • Patent number: 6359627
    Abstract: To select a graphic primitive hidden behind a graphic primitive displayed in foreground, a point on the display screen is pointed to by a pointing device. A CPU detects graphic primitives that include the specified point based on the position and the size indicated by the graphic primitive information stored in the system memory and further detects the smallest graphic primitive completely included in one or more graphic primitives among the detected graphic primitives. The detected smallest graphic primitive is thereafter processed as the selected graphic primitive.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: March 19, 2002
    Assignee: International Business Machines Corporation
    Inventor: Tadashi Someya
  • Patent number: 5524095
    Abstract: In a CMOS type static RAM, a substrate bias voltage VPP higher than a power supply voltage supplied from an outer unit is supplied to an N type substrate region of a PMOS transistor of a CMOS inverter forming a word line driving circuit to bias the N type substrate region to the bias voltage VPP and to a power supply terminal of the CMOS inverter as a power supply voltage. Whereby, resistance of storage data to incidence of radioactive rays is increased just after writing to a storage node of a memory cell is ended, and a soft error generation rate can be easily reduced.
    Type: Grant
    Filed: February 15, 1995
    Date of Patent: June 4, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Someya, Masami Masuda, Satoru Hoshi