Abstract: The magnitude (Ga) of an impact applied to a lens holder is constantly monitored based on an output of an impact sensor. When it is determined that Ga exceeds Gth, focus servo is released, and the lens holder is provided with a force to make it move away from a disk. Upon recheck of Ga, when it is determined that Ga is now equal to or less than Gth, the force having been provided to the lens holder is cancelled, and the focus servo is resumed.

Abstract: When an optical disc is set to the motor, the slice level is set to a slice level Sk as a reference slice level and a measured jitter value A (S0, S1) is produced. The slice level is incremented in steps of a fixed quantity Si (S2). Then, a measured jitter value B obtained at the incremented slice level is compared with the previous measured jitter value A (S3, S4). This sequence of process is repeated, and when the measured jitter value A is smaller than the counter value, it is judged that the jitter changes its quantity varying direction to a decreasing direction. Then, the incrementing operation of the slice level is immediately stopped, and the slice level is decremented in steps of another fixed quantity Sd (<Si). The previous measured jitter value C is compared with a measured jitter value D after the slice level is decremented (S5 to S8). When the measured jitter value C is smaller than the counter jitter value, it is judged that the slice level detected at that time is an optimum slice level.

Abstract: The magnitude (Ga) of an impact applied to a lens holder is constantly monitored based on an output of an impact sensor. When it is determined that Ga exceeds Gth, focus servo is released, and the lens holder is provided with a force to make it move away from a disk. Upon recheck of Ga, when it is determined that Ga is now equal to or less than Gth, the force having been provided to the lens holder is cancelled, and the focus servo is resumed.

Abstract: In an optical disc apparatus of the three-beam type, recording and/or reproduction are performed on an optical disc by: irradiating a groove with a main beam; irradiating a first land where address information of the groove is recorded, in front of the main beam with a first side beam; and irradiating a second land where address information adjacent to the groove is recorded, in rear of the main beam with a second side beam. The optical disc apparatus has: an LLP extracting section 18 which extracts an LLP signal from reflected light of the first side beam that irradiates the first land in front of the main beam; and an MPU 20 which calculates the address information on the basis of the extracted LLP signal, thereby pre-reading the address information.

Abstract: In a disc apparatus, a tracking error signal from an optical pickup is outputted to a micro-computer. The micro-computer discriminates a disc that is different in bit density (track pitch) based on amplitude and/or waveform of the tracking error signal.

Abstract: When a recording medium is mounted in a DVD player, the kind of the recording medium is presumed by detecting the number of recording surfaces and a reflection factor from the output of an optical pick-up, a parameter of a servo control means is set to a parameter of the presumed kind of recording medium (S11) and reading from the recording medium is tried (S12). As a result, in case that the data is readable, the kind of the recording medium is specified (S13). On the other hand, in case that the data is not readable, the parameter of the servo control means is sequentially set to parameters of other kinds of recording mediums (S14, 17), and reading is tried for each setting (S15, 18), whereby the kind of the recording medium is specified (S16, 19).

Abstract: When an optical disc is set to the motor, the slice level is set to a slice level Sk as a reference slice level and a measured jitter value A (S0, S1) is produced. The slice level is incremented in steps of a fixed quantity Si (S2). Then, a measured jitter value B obtained at the incremented slice level is compared with the previous measured jitter value A (S3, S4). This sequence of process is repeated, and when the measured jitter value A is smaller than the counter value, it is judged that the jitter changes its quantity varying direction to a decreasing direction. Then, the incrementing operation of the slice level is immediately stopped, and the slice level is decremented in steps of another fixed quantity Sd (<Si). The previous measured jitter value C is compared with a measured jitter value D after the slice level is decremented (S5 to S8). When the measured jitter value C is smaller than the counter jitter value, it is judged that the slice level detected at that time is an optimum slice level.

Abstract: A disc reading apparatus includes a microcomputer. The microcomputer calculates, based on amount data, an outer radius (RM) of an area that is recording data. The reading speed on the determined outer radius is set to a previously set speed (V.sub.2) for the outer circumference. When reading desired data, a radius of an inner circumference (r) of the data-recorded area is calculated from time information (identification data) to calculate a reading speed (V.sub.n) for reading the data. That is, since the disc contains data recorded such that the linear velocity per unit area becomes constant, the position of a pick-up and the reading speed are represented by a generally inversely proportional linear equation. Therefore, the reading speed (V.sub.n) can be calculated based on the inner radius (r) of the area recording the data to be read, the inner and outer radii (RS, RM) of the data-recorded area, and previously set inner and outer speeds (V.sub.1, V.sub.2).

Abstract: A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240).

Abstract: A circuit is designed with a first lower conductor (500) having two ends. One end of the first lower conductor is coupled to a first signal source (386). A first upper conductor (544) has two ends and is spaced apart from the first lower conductor by a distance less than an allowable spacing between adjacent lower conductors. One end of the first upper conductor is coupled to a second signal source (384). A second upper conductor (508) has two ends. One end of the second upper conductor is coupled to another end of the first lower conductor for receiving a signal from the first signal source. A second lower conductor (552) has two ends and is spaced apart from the second upper conductor by a distance less than the allowable spacing between adjacent lower conductors. One end of the second lower conductor is coupled to another end of the first upper conductor for receiving a signal from the second signal source.

Abstract: A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14.

Abstract: A semiconductor memory device which has a memory portion and a counter to count rows and/or columns of the memory portion, the counter being so constructed to return to a reset mode at the beginning of an address counting sequence when coming up to an arbitrary address such that an address or addresses corresponding to a region of the memory containing one or more defective memory cells and occurring after the arbitrary address are inaccessible. The counter thereby comprises a defective bit relief circuit built into the memory device.

Abstract: A memory device including a voltage stepdown circuit is proposed in which a reduced reference voltage is produced from a supplied reference voltage and is passed to the selected one of the row lines of the memory array after all the row lines are discharged to ground potential, while the supplied reference voltage is fed directly, viz., without reduction, to all the control circuits of the device. The voltage stepdown circuit provided in the memory device is thus relieved from the burden to supply current to the control circuits and has only to feed the selected one of the row lines so that the field-effect transistors forming the voltage stepdown circuit can be fabricated to have channel regions with significantly reduced widths.

Abstract: A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.