Patents by Inventor Tadashi Tojo

Tadashi Tojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147617
    Abstract: A wiring body disposed above a substrate including a conductor including: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A lower layer included in the via electrode and located above the insulating layer and a lower layer included in the wiring include the same material.
    Type: Application
    Filed: March 16, 2022
    Publication date: May 2, 2024
    Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
  • Publication number: 20240145374
    Abstract: A wiring body disposed above a substrate including a conductor includes: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. The via electrode includes: a seed layer formed along an inner surface of the insulating layer from above the conductor in the via hole; a via electrode body layer formed to be located above the seed layer and fill the via hole; and an adhesion layer formed between the seed layer and the inner surface of the insulating layer in the via hole.
    Type: Application
    Filed: March 16, 2022
    Publication date: May 2, 2024
    Inventors: Takayoshi NIRENGI, Akihiro OISHI, Tsutomu AISAKA, Daisuke MATSUSHITA, Jumpei IWANAGA, Tadashi TOJO
  • Patent number: 7816611
    Abstract: After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: October 19, 2010
    Assignee: Panasonic Corporation
    Inventors: Toshiaki Takenaka, Yoshihiro Kawakita, Tadashi Tojo, Kiyohide Tatsumi
  • Publication number: 20070107931
    Abstract: After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
    Type: Application
    Filed: January 4, 2007
    Publication date: May 17, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiaki Takenaka, Yoshihiro Kawakita, Tadashi Tojo, Kiyohide Tatsumi
  • Patent number: 7181839
    Abstract: After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
    Type: Grant
    Filed: December 26, 2003
    Date of Patent: February 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiaki Takenaka, Yoshihiro Kawakita, Tadashi Tojo, Kiyohide Tatsumi
  • Publication number: 20050006139
    Abstract: After disposing metallic foils on either surface of a prepreg sheet of low compressibility having conducting holes filled with conductive paste, the prepreg sheet is compressed in a state of being kept at a relatively low temperature, and after that, the temperature is raised under pressure to melt and harden the resin in the prepreg sheet, and thereby, the connecting resistance is stabilized, and a high-quality circuit board can be obtained.
    Type: Application
    Filed: December 26, 2003
    Publication date: January 13, 2005
    Inventors: Toshiaki Takenaka, Yoshihiro Kawakita, Tadashi Tojo, Kiyohide Tatsumi