Abstract: An integrated circuit device includes a drive circuit that outputs a first drive waveform signal for dot matrix display and a second drive waveform signal for segment display, a first output terminal, a second output terminal, and a control circuit that controls the drive circuit. The drive circuit outputs the first drive waveform signal to the first output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the first output terminal when its terminal is set as the output terminal for segment display. The drive circuit outputs the first drive waveform signal to the second output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the second output terminal when its terminal is set as the output terminal for segment display.

Abstract: An integrated circuit device includes a voltage supply circuit and a drive circuit. The voltage supply circuit supplies a common voltage, a first positive polarity voltage higher than the common voltage, a second positive polarity voltage higher than the first positive polarity voltage, a first negative polarity voltage lower than the common voltage, and a second negative polarity voltage lower than the first negative polarity voltage. The drive circuit outputs a first drive waveform signal for dot matrix display based on the common voltage, the first positive polarity voltage, the second positive polarity voltage, the first negative polarity voltage, and the second negative polarity voltage, and outputs a second drive waveform signal for segment display based on the common voltage, the first positive polarity voltage, and the first negative polarity voltage.

Abstract: An integrated circuit device includes a drive circuit that outputs a first drive waveform signal for dot matrix display and a second drive waveform signal for segment display, a first output terminal, a second output terminal, and a control circuit that controls the drive circuit. The drive circuit outputs the first drive waveform signal to the first output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the first output terminal when its terminal is set as the output terminal for segment display. The drive circuit outputs the first drive waveform signal to the second output terminal when its terminal is set as the output terminal for dot matrix display, and outputs the second drive waveform signal to the second output terminal when its terminal is set as the output terminal for segment display.

Abstract: An integrated circuit device includes a voltage supply circuit and a drive circuit. The voltage supply circuit supplies a common voltage, a first positive polarity voltage higher than the common voltage, a second positive polarity voltage higher than the first positive polarity voltage, a first negative polarity voltage lower than the common voltage, and a second negative polarity voltage lower than the first negative polarity voltage. The drive circuit outputs a first drive waveform signal for dot matrix display based on the common voltage, the first positive polarity voltage, the second positive polarity voltage, the first negative polarity voltage, and the second negative polarity voltage, and outputs a second drive waveform signal for segment display based on the common voltage, the first positive polarity voltage, and the first negative polarity voltage.

Abstract: There is disclosed a liquid crystal driving device which improves crosstalk using the function of adjusting an interlaced line number of common electrodes and the function of adjusting a polarity reversion line number.

Abstract: There is disclosed a liquid crystal driving device which improves crosstalk using the function of adjusting an interlaced line number of common electrodes and the function of adjusting a polarity reversion line number.

Abstract: A driving method of an electro optical device for driving with an Multi Line Selection driving method includes a gradation parameter assigning step of assigning display data of N bits (N is an integer equal to or larger than two) to a gradation parameter of M bits (N<M, M is an integer equal to or larger than three), and a driving step of applying a driving voltage in accordance with an Frame Rate Control pattern selected on the basis of the gradation parameter to the segment electrodes in a divided period in association with the gradation parameter assigned at the gradation parameter assigning step out of periods provided by dividing a selection period of common electrodes simultaneously selected.

Abstract: A display driver includes: a decoder which decodes n-bit (n is an integer greater than one) display data sequentially input from a display memory in units of n bits; a plurality of latch circuits which latch output data of the decoder; an address decoder which generates a latch pulse for the latch circuits to latch output from the decoder; and a plurality of data line driver sections. The n-bit display data is read from the display memory and input to the decoder by performing wordline control once. The decoder decodes the n-bit display data, and sequentially outputs the decoded data to the latch circuits. The address decoder outputs the latch pulse to one of the latch circuits selected based on address information on the display memory when the n-bit display data is read and storage destination designation information arbitrarily set from a control circuit.

Abstract: A display driver includes: a parity generation circuit which generates s-bit parity data for n-bit display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit which performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder which decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits which latch the data decoded by the decoder; and a plurality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits.

Abstract: A display driver includes: a decoder which decodes n-bit (n is an integer greater than one) display data sequentially input from a display memory in units of n bits; a plurality of latch circuits which latch output data of the decoder; an address decoder which generates a latch pulse for the latch circuits to latch output from the decoder; and a plurality of data line driver sections. The n-bit display data is read from the display memory and input to the decoder by performing wordline control once. The decoder decodes the n-bit display data, and sequentially outputs the decoded data to the latch circuits. The address decoder outputs the latch pulse to one of the latch circuits selected based on address information on the display memory when the n-bit display data is read and storage destination designation information arbitrarily set from a control circuit.

Abstract: A display driver including: a decoder which decodes n-bit display data (n is an integer greater than one) sequentially input from a display memory in units of n bits; a plurality of latch circuits which latch output data from the decoder, and a pluality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits. The n-bit display data is read from the display memory and output to the decor by performing wordline control once for the display memory. The decoder squentially outputs the decoded n-bit display data to the latch circuits. The data line driver sections drive the data lines after the decoded data has been stored in the latch circuits.

Abstract: A display driver includes: a parity generation circuit which generates s-bit parity data for n-bit display data input through a processor interface, combines the n-bit display data and the s-bit parity data, and outputs the combined n-bit display data and s-bit parity data to a display memory as (n+s)-bit display data; a parity check circuit which performs data error detection for the (n+s)-bit display data sequentially input from the display memory in units of (n+s) bits, and outputs the n-bit display data; at least one decoder which decodes the n-bit display data output from the parity check circuit; a plurality of latch circuits which latch the data decoded by the decoder; and a plurality of data line driver sections which drive data lines of a display panel based on the data latched by the latch circuits.

Abstract: A liquid crystal driver IC comprising: a power circuit; an electric volume for varying an output voltage from the power circuit; a temperature detector; and a correction table for storing an electric volume control value corresponding to a temperature detected by the temperature detector. The power circuit includes: a first power circuit having a first temperature-voltage characteristic; a second power circuit having a second temperature-voltage characteristic; and a temperature gradient selection circuit for outputting a voltage conforming with a desired temperature gradient characteristic based on output voltages from the first and second power circuits. The temperature detector detects an actual temperature based on the first and second temperature-voltage characteristics.

Abstract: A power supply device for driving liquid crystal which generates four liquid crystal drive voltages V1 and V4 between first and second reference voltages, the power supply device comprising: a voltage division circuit 102 which divides a voltage between voltages between voltages V1 and V5 and generates four pairs of first voltages NV1 to NV4 and second voltages PV1 to PV4; and four impedance conversion circuits 103 and 104 which generate impedance converted liquid crystal drive voltages V1 to V4 based on the four pairs of the first and second voltages. Each impedance conversion circuit comprises voltage follower type of differential amplifier circuits 120 and 110 to which a pair of the first and second voltages is input, and an output circuit 130 which is driven by the differential amplification circuits. The N-type transistor 134 and P-type transistor 132 in the output circuit are independently driven by the first and second output voltages VN, VP from the differential amplification circuits 120 and 110.

Abstract: A display driver IC which adopts a serial transmission system to reduce the number of terminal pins, transmits a command and data efficiently and also can speed-up data transmission. The display driver IC comprises an interface circuit to which signals from an external MPU are input, a command decoder for decoding command data input from the external MPU through the interface circuit, a storage section in which display data input from the external MPU through the interface circuit is written; and a display driving section for driving a display on the basis of the display data written in the storage section. The interface circuit comprises a first input terminal to which a serial data input signal is input, a second input terminal to which a serial clock signal is input and a third input terminal to which a chip select signal is input.

Abstract: A DC-DC voltage boosting method is capable of reducing power consumption by detecting a margin of a boosting voltage, even if the display mode of a liquid crystal panel or a displayed content changes. Included are the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) generating a stabilized operating voltage by using the boosted voltage, (c) detecting a margin voltage between the boosted voltage and the operating voltage, and (d) based on the detected result in step (c), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.

Abstract: A power supply device for driving liquid crystal which generates four liquid crystal drive voltages V1 and V4 between first and second reference voltages, the power supply device comprising: a voltage division circuit 102 which divides a voltage between voltages between voltages V1 and V5 and generates four pairs of first voltages NV1 to NV4 and second voltages PV1 to PV4; and four impedance conversion circuits 103 and 104 which generate impedance converted liquid crystal drive voltages V1 to V4 based on the four pairs of the first and second voltages. Each impedance conversion circuit comprises voltage follower type of differential amplifier circuits 120 and 110 to which a pair of the first and second voltages is input, and an output circuit 130 which is driven by the differential amplification circuits. The N-type transistor 134 and P-type transistor 132 in the output circuit are independently driven by the first and second output voltages VN, VP from the differential amplification circuits 120 and 110.

Abstract: A power supply device for driving liquid crystal which generates four liquid crystal drive voltages V1 and V4 between first and second reference voltages, the power supply device comprising: a voltage division circuit 102 which divides a voltage between voltages between voltages V1 and V5 and generates four pairs of first voltages NV1 to NV4 and second voltages PV1 to PV4; and four impedance conversion circuits 103 and 104 which generate impedance converted liquid crystal drive voltages V1 to V4 based on the four pairs of the first and second voltages. Each impedance conversion circuit comprises voltage follower type of differential amplifier circuits 120 and 110 to which a pair of the first and second voltages is input, and an output circuit 130 which is driven by the differential amplification circuits. The N-type transistor 134 and P-type transistor 132 in the output circuit are independently driven by the first and second output voltages VN, VP from the differential amplification circuits 120 and 110.

Abstract: A DC-DC voltage boosting method is capable of reducing power consumption by detecting a margin of a boosting voltage, even if the display mode of a liquid crystal panel or a displayed content changes. Included are the steps of (a) boosting an input voltage by using clock signals to generate a boosted voltage, (b) generating a stabilized operating voltage by using the boosted voltage, (c) detecting a margin voltage between the boosted voltage and the operating voltage, and (d) based on the detected result in step (c), adjusting the frequency of the clock signals used in step (a) or fixing at least one of the clock signals which control switching components.

Abstract: A wireless selective-call receiver makes use of detection or absence of any to-and-fro movement of the receiver indicating that the receiver has been left somewhere thereby improving the security function of the receiver. When a motion detector detects no continuous shaky movement of the receiver, the message received by the receiver is stored in memory. A controller comprises a first control section which operates in a no movement condition, a second control section which operates in a moving condition, and a switching means for switching from the first control section to the second control section and vice versa. In the absence of the to-and-fro movement of the receiver (for example, the receiver is put away from the owner's body to be left on the desk), any access through a button inputting console and external interface except inputting a password is rejected. The message received is stored in memory, and not given on display, thereby preventing pieces of private information from leaking.