Patents by Inventor Tadayoshi Miyamoto

Tadayoshi Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12120915
    Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 15, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura, Kayo Haruguchi
  • Publication number: 20240334741
    Abstract: A display device includes: a resin substrate, and a thin film transistor layer, wherein in the thin film transistor layer, a first thin film transistor and a second thin film transistor are provided for each of subpixels. The first thin film transistor includes a first semiconductor layer formed of polysilicon, a first gate electrode provided on the resin substrate side of the first semiconductor layer via a first gate insulating film, and a metal layer provided on a side opposite to the resin substrate side of the first semiconductor layer via a first interlayer insulating film. The second thin film transistor includes a second semiconductor layer formed of an oxide semiconductor, and a second gate electrode provided on a side opposite to the resin substrate of the second semiconductor layer via a second gate insulating film.
    Type: Application
    Filed: October 11, 2021
    Publication date: October 3, 2024
    Inventors: Tadayoshi MIYAMOTO, Sohtaroh TANAKA, Fumie YASHIRO
  • Publication number: 20240292676
    Abstract: A first TFT includes: a first semiconductor layer of a polysilicon; and a first gate electrode on the first semiconductor layer via a first gate insulating film. A second TFT includes: a first conductive layer and a second conductive layer made of the same material, and provided in the same layer, as the first semiconductor layer; a second semiconductor layer of an oxide semiconductor on the first conductive layer and the second conductive layer; and a second gate electrode on the second semiconductor layer via the second gate insulating film.
    Type: Application
    Filed: August 18, 2021
    Publication date: August 29, 2024
    Inventors: Tadayoshi MIYAMOTO, Yoshinobu NAKAMURA, Toshihiro KANEKO
  • Publication number: 20240276795
    Abstract: A first TFT includes: a first semiconductor layer formed of polysilicon; and a first gate electrode provided to the first semiconductor layer toward a resin substrate through a first gate insulating film. A second TFT includes: a second semiconductor layer formed of oxide semiconductor and positioned more distant from the resin substrate than the first semiconductor layer; and a second gate electrode provided to the second semiconductor layer across from the resin substrate through a second gate insulating film.
    Type: Application
    Filed: July 13, 2021
    Publication date: August 15, 2024
    Inventor: Tadayoshi MIYAMOTO
  • Publication number: 20240040836
    Abstract: A first TFT includes a first semiconductor layer formed of polysilicon, a gate insulating film provided on the first semiconductor layer, a third semiconductor layer provided on the gate insulating film, and a first gate electrode provided on the third semiconductor layer, and a second TFT includes a second semiconductor layer formed of an oxide semiconductor, a first metal layer and a second metal layer formed on a third conductor region and a fourth conductor region, respectively, of the second semiconductor layer.
    Type: Application
    Filed: December 8, 2020
    Publication date: February 1, 2024
    Inventor: TADAYOSHI MIYAMOTO
  • Patent number: 11774819
    Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: October 3, 2023
    Assignee: Sharp Display Technology Corporation
    Inventors: Tadayoshi Miyamoto, Yoshitaka Koyama, Yoshinobu Nakamura, Toshihiro Kaneko
  • Publication number: 20230244114
    Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.
    Type: Application
    Filed: January 11, 2023
    Publication date: August 3, 2023
    Inventors: Tadayoshi MIYAMOTO, Yoshitaka KOYAMA, Yoshinobu NAKAMURA, Toshihiro KANEKO
  • Patent number: 11437520
    Abstract: The transistor includes a first insulating film, an oxide semiconductor layer, a gate insulating film, an upper gate electrode, and a second insulating film being sequentially layered on a substrate, and the transistor includes a light blocking layer layered on the second insulating film and formed of metal. The light blocking layer is electrically connected to the upper gate electrode by interposing a gate contact hole provided in the second insulating film. The oxide semiconductor layer is configured such that a region overlapping with the upper gate electrode entirely overlaps with the light blocking layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: September 6, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura
  • Publication number: 20220115479
    Abstract: A display device includes a drive transistor and a switching transistor formed by layering an inorganic insulating film, an oxide semiconductor layer, an upper gate insulating layer, an upper gate electrode, and an interlayer insulating film. The drive transistor and the switching transistor include an oxide semiconductor film formed of the oxide semiconductor layer and provided in an island shape corresponding to the drive transistor and an island shape corresponding to the switching transistor, and the oxide semiconductor film includes a channel region overlapping with the upper gate electrode corresponding to the oxide semiconductor film, and a source region and a drain region. The drive transistor is provided with a lower gate electrode and a lower gate insulating layer between the inorganic insulating film and the oxide semiconductor layer. The length of lower gate electrode is less than or equal to the length of upper gate electrode.
    Type: Application
    Filed: September 18, 2018
    Publication date: April 14, 2022
    Inventors: TADAYOSHI MIYAMOTO, YOSHINOBU NAKAMURA, KAYO HARUGUCHI
  • Publication number: 20220093650
    Abstract: A display device includes a transistor including: a substrate; a lower electrode; a lower insulating film; an oxide semiconductor layer; a gate insulating film; and a gate electrode stacked on top of an other in a stated order. The gate electrode matches the gate insulating film in plan view. The oxide semiconductor layer includes: a channel region across the gate insulating film from the gate electrode; and a source region and a drain region provided to sandwich the channel region. The lower electrode extends to intersect with the oxide semiconductor layer in plan view. The lower electrode has: a source-side end face positioned toward the source region and overlap with the source region; and a drain-side end face positioned toward the drain region and overlap with the channel region.
    Type: Application
    Filed: February 4, 2019
    Publication date: March 24, 2022
    Inventors: TADAYOSHI MIYAMOTO, KAYO HARUGUCHI, YOSHINOBU NAKAMURA
  • Patent number: 10950705
    Abstract: An active matrix substrate includes a peripheral circuit including a TFT (30A) supported on a substrate (1). When viewed in a direction normal to the substrate (1), a first gate electrode (3) of the TFT (30A) includes a first edge portion and a second edge portion (3e1, 3e2) opposing each other. The first edge portion and the second edge portion extend across an oxide semiconductor layer (7) in a channel width direction. At least one of the first edge portion and the second edge portion includes, in a region overlapping with the oxide semiconductor layer (7), a first recess portion (40) recessed in a channel length direction and a first part (41) adjacent to the first recess portion in the channel width direction. When viewed in the direction normal to the substrate (1), a source electrode (8) or a drain electrode (9) of the TFT (30A) overlaps with at least a part of the first recess portion (40) and at least a part of the first part (41).
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: March 16, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tadayoshi Miyamoto
  • Publication number: 20210057583
    Abstract: The transistor includes a first insulating film, an oxide semiconductor layer, a gate insulating film, an upper gate electrode, and a second insulating film being sequentially layered on a substrate, and the transistor includes a light blocking layer layered on the second insulating film and formed of metal. The light blocking layer is electrically connected to the upper gate electrode by interposing a gate contact hole provided in the second insulating film. The oxide semiconductor layer is configured such that a region overlapping with the upper gate electrode entirely overlaps with the light blocking layer.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 25, 2021
    Inventors: TADAYOSHI MIYAMOTO, YOSHINOBU NAKAMURA
  • Publication number: 20200185527
    Abstract: A gate driver TFT 30 includes a first gate electrode 30a formed from a first metal film 15, a second gate electrode 31 formed from a second metal film 19 and overlapping a part of the first gate electrode 30a, an electrode 32 formed from the second metal film 19 overlapping a part of the first gate electrode 30a and disposed away from the second gate electrode 31 at an interval, channel portions 30d formed from the oxide semiconductor film 17 and one of which overlaps the second gate electrode 31 and another one of which overlaps the electrode 32, and a first low-resistance portion 33 formed from the oxide semiconductor film 17, the first-low resistance portion not overlapping the second gate electrode 31 and the electrode 32 and disposed between at least the channel portions 30d and having a resistance lower than that of the channel portions 30d.
    Type: Application
    Filed: April 20, 2017
    Publication date: June 11, 2020
    Inventor: Tadayoshi MIYAMOTO
  • Patent number: 10571761
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes a plurality of DMX circuit TFTs. Each of the DMX circuit TFTs includes a front-gate electrode (FG) supplied with a control signal from one of a plurality of control signal main lines ASW, BSW and a back-gate electrode (BG) supplied with a back-gate signal which is different from the control signal. The plurality of DMX circuit TFTs includes first DMX circuit TFTs (T1a, T1b) and second DMX circuit TFTs (T2a, T2b). The back-gate electrode of each of the first DMX circuit TFTs (T1a, T1b)is connected with a first back-gate signal main line (BGL(1)) which supplies a first back-gate signal and, the back-gate electrode of each of the second DMX circuit TFTs (T2a, T2b)is connected with a second back-gate signal main line (BGL(2)) which supplies a second back-gate signal which is different from the first back-gate signal.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Akihiro Oda, Tadayoshi Miyamoto
  • Publication number: 20200052083
    Abstract: An active matrix substrate includes a peripheral circuit including a TFT (30A) supported on a substrate (1). When viewed in a direction normal to the substrate (1), a first gate electrode (3) of the TFT (30A) includes a first edge portion and a second edge portion (3e1, 3e2) opposing each other. The first edge portion and the second edge portion extend across an oxide semiconductor layer (7) in a channel width direction. At least one of the first edge portion and the second edge portion includes, in a region overlapping with the oxide semiconductor layer (7), a first recess portion (40) recessed in a channel length direction and a first part (41) adjacent to the first recess portion in the channel width direction. When viewed in the direction normal to the substrate (1), a source electrode (8) or a drain electrode (9) of the TFT (30A) overlaps with at least a part of the first recess portion (40) and at least a part of the first part (41).
    Type: Application
    Filed: February 6, 2018
    Publication date: February 13, 2020
    Inventor: Tadayoshi MIYAMOTO
  • Patent number: 10558097
    Abstract: In a demultiplexer circuit, each unit circuit includes at least n TFTs 30 and n branch lines connected with one video signal line. Each TFT 30 includes an oxide semiconductor layer 7, an upper gate electrode 11 provided on the oxide semiconductor layer with a gate insulating layer 9 interposed therebetween, and a first electrode 13 and a second electrode 15. The demultiplexer circuit further includes a first interlayer insulating layer 21 covering the oxide semiconductor layer and the upper gate electrode and a second interlayer insulating layer 23 provided on the first interlayer insulating layer. The first electrode 13 is provided between the first interlayer insulating layer 21 and the second interlayer insulating layer 23 and is in contact with the oxide semiconductor layer inside a first contact hole CH1 formed in the first interlayer insulating layer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: February 11, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Yoshinobu Nakamura
  • Patent number: 10438973
    Abstract: This display device is provided with: a circuit substrate having a display region and a non-display region; pixel-driving TFTs for driving pixels, formed in the display region and having source electrodes and drain electrodes being spaced apart from each other on an insulating film and a first active layer formed from an oxide semiconductor, provided on the opposite side from the insulating film so as to cover a separation section between a source electrode and a drain electrode and part of the source electrode and part of the drain electrode adjacent to the separation section; and a driver circuit TFT for driving the pixel-driving TFTs, formed in the non-display region and having a second active layer formed from a non-oxide semiconductor.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 8, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Fumiki Nakano
  • Patent number: 10367009
    Abstract: Provided is an active-matrix substrate in which the line resistance is decreased. The active-matrix substrate includes a substrate 31, a plurality of gate lines Gj disposed on the substrate 31 and extending in a first direction, a plurality of source lines Si disposed on the substrate 31 and extending in a second direction different from the first direction, a transistor 2 disposed correspondingly to each of intersection points of the gate lines and the source lines Si and connected to a corresponding one of the gate lines Gj and a corresponding one of the source lines Si, an insulating layer, and extended conductive films 51, 52, and 61. At least ones of the gate lines Gj and the source lines Si each have a layered structure with connection to the extended conductive film via a contact hole provided in the insulating layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: July 30, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tadayoshi Miyamoto, Fumiki Nakano
  • Patent number: 10355040
    Abstract: An off-leakage current of a photodiode is reduced in a photoelectric conversion device. A photoelectric conversion device (100) includes: an oxide semiconductor layer (5) provided on a substrate (1); a passivation film (6) and a planarizing film (7) which are stacked on the oxide semiconductor layer; and a photodiode (9) including a lower electrode (91), a photoelectric conversion layer (92), and an upper electrode (93). The lower electrode is connected to a source electrode (4) via a contact hole provided in the passivation film and the planarizing film. No photoelectric conversion layer is provided directly above the contact hole.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 16, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuatsu Ito, Seiji Kaneko, Yohsuke Kanzaki, Takao Saitoh, Tadayoshi Miyamoto
  • Publication number: 20190131459
    Abstract: A gate driver TFT 30 includes: a gate electrode 30a; a channel portion 30d overlapping the gate electrode 30a with a gate insulating film 16 disposed therebetween and constructed from an oxide semiconductor film 17 that is a semiconductor film; a source electrode 30b connected to one end of the channel portion 30d; a drain electrode 30c connected to another end of the channel portion 30d; and an intermediate electrode 22 connected to the channel portion 30d at a position at which a distance L1 to the drain electrode 30c is greater than a distance L2 to the source electrode 30b.
    Type: Application
    Filed: April 7, 2017
    Publication date: May 2, 2019
    Inventors: Tadayoshi MIYAMOTO, Akihiro ODA