Patents by Inventor Tadayoshi Nakatsuka

Tadayoshi Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8193091
    Abstract: The present invention includes a die pad; signal leads, ground connection leads connected to the die pad; a semiconductor chip including electrode pads for grounding; metal thin wires, and an encapsulating resin for encapsulating the die pad and the semiconductor chip and encapsulating the signal leads and the ground connection lead such that lower portions of the signal leads and the ground connection lead are exposed as external terminals. The ground connection lead is connected to the electrode pad for grounding, so that the resin-encapsulated semiconductor device is electrically stabilized. Furthermore, interference between high frequency signals passing through the signal leads can be suppressed by the die pad and the ground connection leads.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: June 5, 2012
    Assignee: Panasonic Corporation
    Inventors: Fumihiko Kawai, Toshiyuki Fukuda, Masanori Minamio, Noboru Takeuchi, Shuichi Ogata, Katsushi Tara, Tadayoshi Nakatsuka
  • Publication number: 20100225378
    Abstract: A radio frequency switching circuit includes: a first switching element; a second switching element; a first biasing resistive element connected to a control terminal of the first switching element; a second biasing resistive element connected to a control terminal of the second switching element; and a control circuit which controls the first switching element and the second switching element according to a control signal being output from a control signal output terminal. C1>C2, and Rb 1<Rb2 are satisfied, where the capacitance of the control terminal of the first switching element is C1, the capacitance of the control terminal of the second switching element is C2, the resistance value of the first biasing resistive element is Rb1, and the resistance value of the second biasing resistive element 204a is Rb2.
    Type: Application
    Filed: February 22, 2010
    Publication date: September 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Tadayoshi NAKATSUKA, Shinji YAMAMOTO
  • Patent number: 7636004
    Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: December 22, 2009
    Assignee: Panasonic Corporation
    Inventors: Tadayoshi Nakatsuka, Katsushi Tara, Shinji Fukumoto
  • Patent number: 7541860
    Abstract: When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: June 2, 2009
    Assignee: Panasonic Corporation
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka
  • Publication number: 20090086394
    Abstract: In a circuit in which a protected element 42 is connected between an input terminal 61 and an output terminal 62, and a protected element 41 is connected between the input terminal 61 and a reference potential terminal 71, the protected element 41 and a protection circuit 51 are connected in parallel with each other. The protection circuit 51 includes: a field-effect transistor (FET) 11 having a drain connected to the input terminal 61 and a source connected to the reference potential terminal 71; a resistance 31 having one end connected to a gate of the FET 11; a resistance 32 for connecting the other end of the resistance 31 to the source of the FET 11; and a capacitor 21 for connecting the other end of the resistance 31 to the drain of the FET 11.
    Type: Application
    Filed: September 24, 2008
    Publication date: April 2, 2009
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka
  • Patent number: 7492238
    Abstract: A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: February 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Tadayoshi Nakatsuka, Atsushi Suwa, Motoo Nakagawa, Masakazu Adachi
  • Publication number: 20080218240
    Abstract: When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 11, 2008
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka
  • Patent number: 7423499
    Abstract: A high-frequency switching apparatus is composed of a transfer circuit unit including a plurality of FETs, and a shunt circuit unit including a plurality of FETs, as well. An electromagnetic wave absorption material element is connected to an end of the shunt circuit unit. To a connection point between the shunt circuit unit and the electromagnetic wave absorption material element, an external voltage terminal for fixing a potential at the point is connected. By this, a high-frequency switching apparatus is obtained which is excellent in isolation characteristics and is hard to break down even when a signal of a high voltage, such as an electrostatic surge, flows into the apparatus.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masakazu Adachi, Tadayoshi Nakatsuka
  • Patent number: 7391282
    Abstract: Switch sections composed of a plurality of FETs 111 to 118 and 121 to 128 connected in series are provided between input/output terminals 161 and 162 and ground terminals 181 and 182, and between the input/output terminals 161 to 163. A plurality of gate bias resistors 131 to 138, 141 to 148 are also provided. One terminal of each gate bias resistor is connected to a gate electrode of a corresponding one of the FETs 111 to 118 and 121 to 128, while a control voltage 171 and 172 for switching an ON state and an OFF state of the switch section is applied to the other terminal. Among the FETs included in each switch section, concerning the FETs 114, 115, 124, and 125 to which signal power is applied when the switch section is in the OFF state, the gate bias resistors 134, 135, 144, and 145 connected to the gate electrodes are set to have a highest resistance value.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: June 24, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Masashi Miyagi
  • Patent number: 7337547
    Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Yasuda, Kenichi Hidaka, Yasuyuki Masumoto, Tadayoshi Nakatsuka, Atsushi Watanabe, Katsushi Tara
  • Publication number: 20070290744
    Abstract: The present invention provides an inexpensive radio frequency switching circuit having desirable radio frequency characteristics over a wide band and desirable endurance against the inflow of a high voltage signal such as an electrostatic surge. Either a negative bias voltage or a positive bias voltage being greater than or equal to 0V and less than or equal to a Schottky forward voltage is used for the control terminals V11 and V12 for controlling FETs 11 to 18 and FETs 21 to 28 so as to turn ON/OFF the path extending from the first input/output terminal P11 to the second input/output terminal P12 and the path extending from the first input/output terminal P11 to the third input/output terminal P13. Thus, it is possible to eliminate the need for DC cut capacitors.
    Type: Application
    Filed: May 31, 2007
    Publication date: December 20, 2007
    Inventors: Masakazu Adachi, Tadayoshi Nakatsuka
  • Patent number: 7286001
    Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Katsushi Tara, Shinji Fukumoto
  • Patent number: 7265604
    Abstract: A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: September 4, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka
  • Publication number: 20070139094
    Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
    Type: Application
    Filed: February 7, 2007
    Publication date: June 21, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tadayoshi Nakatsuka, Katsushi Tara, Shinji Fukumoto
  • Patent number: 7221207
    Abstract: A semiconductor apparatus is provided which makes it possible to reduce the number of control terminals required for switching through paths of a high frequency signal, simplify the circuit configuration for controlling the terminals, improve an isolation characteristic between on path and off path of a through FET, and obtain a sufficiently high isolation. In this semiconductor apparatus, one specific through FET and each of shunt FETs connected to each of through FETs other than the one specific through FET are simultaneously turned on in response to the same control signal inputted to the same control terminal. Thus, when a high frequency signal leaks from an output terminal to the signal path of the through FET having been turned on, through the signal paths of the through FETs having been turned off, the high frequency signal can be released to GND through the shunt FET having been turned on.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: May 22, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shinji Fukumoto, Katsushi Tara, Tadayoshi Nakatsuka, Tomohiko Nakamura
  • Publication number: 20070102730
    Abstract: An RF switching circuit according to the present invention includes: a plurality of input/output terminals for inputting and outputting an RF signal; and a switch for opening and closing an electrical connection between the input/output terminals. The switch is constituted by a multi-gate field effect transistor including a plurality of gates located between source and drain spaced from each other on a semiconductor layer. A bias voltage is applied to an inter-gate region of the semiconductor layer between the gates. The bias voltage is equal to or lower than 90% of a high-level voltage, which is a voltage for turning the multi-gate field effect transistor ON, in a state where the multi-gate field effect transistor is ON, and is equal to or higher than 80% of the high-level voltage and equal to or lower than the high-level voltage in a state where the multi-gate field effect transistor is OFF.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Shinji Fukumoto
  • Publication number: 20070103252
    Abstract: A common terminal 500 is connected to drains of FETs 101 and 102 via a capacitor 400. FETs 111 to 114 are serially connected, and inserted between a source of the FET 101 and a terminal 501 via a capacitor 401. Similarly, each of: FETs 121 to 124; FETs 131 to 133; FETs 141 to 143; FETs 151 to 153; and FETs 161 to 163 is inserted between the source of the FET 101 or an FET 102 and a corresponding one of terminals 502 to 506. This configuration allows a stray capacitance value of a transmission/reception path to be reduced at the time of transmission/reception, thereby obtaining a favorable radio-frequency characteristic.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Inventors: Tadayoshi Nakatsuka, Atsushi Suwa, Motoo Nakagawa, Masakazu Adachi
  • Publication number: 20070096845
    Abstract: A high-frequency switching apparatus is composed of a transfer circuit unit including a plurality of FETs, and a shunt circuit unit including a plurality of FETs, as well. An electromagnetic wave absorption material element is connected to an end of the shunt circuit unit. To a connection point between the shunt circuit unit and the electromagnetic wave absorption material element, an external voltage terminal for fixing a potential at the point is connected. By this, a high-frequency switching apparatus is obtained which is excellent in isolation characteristics and is hard to break down even when a signal of a high voltage, such as an electrostatic surge, flows into the apparatus.
    Type: Application
    Filed: October 12, 2006
    Publication date: May 3, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masakazu Adachi, Tadayoshi Nakatsuka
  • Publication number: 20070085592
    Abstract: In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 ?sec or more at the time of switching from a boosted voltage to a non-boosted voltage.
    Type: Application
    Filed: September 11, 2006
    Publication date: April 19, 2007
    Inventors: Eiji Yasuda, Tadayoshi Nakatsuka, Toshihiro Shougaki, Kenichi Hidaka, Taketo Kunihisa
  • Patent number: 7199635
    Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: April 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tadayoshi Nakatsuka, Katsushi Tara, Shinji Fukumoto