Patents by Inventor Tadayoshi Okuda

Tadayoshi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955935
    Abstract: The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: April 9, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tadayoshi Okuda
  • Publication number: 20230109304
    Abstract: A playback device (measurement device) in a record playback system including a record player and the playback device measures a frequency characteristic of each of a plurality of input signals which are input from the record player to the playback device when a plurality of test signals for measuring a characteristic of the record playback system are played back by the record player, the plurality of test signals being recorded on a phonograph record, the plurality of input signals corresponding to the plurality of test signals recorded; calculates a measurement error between the frequency characteristic of each of the plurality of input signals measured and a predetermined frequency characteristic; selects a frequency characteristic of which the measurement error is smallest from among the frequency characteristics of the plurality of input signals, as a measurement result of the record playback system; and outputs the measurement result selected.
    Type: Application
    Filed: November 6, 2020
    Publication date: April 6, 2023
    Inventor: Tadayoshi OKUDA
  • Publication number: 20220103138
    Abstract: The signal processing device includes: an offset adjuster; an amplitude adjuster; and a delay adjuster, wherein the offset adjuster adjusts the DC offset using a first parameter regarding the DC offset determined based on an output of the offset adjuster which is output when no signal is input to the signal processing circuit by the subtractor, the amplitude adjuster adjusts the amplitude using a second parameter regarding the amplitude determined based on (i) an output of the amplitude adjuster which is output when a first test signal is input to the signal processing circuit and (ii) the first test signal, and the delay adjuster adjusts the delay using a third parameter regarding the delay determined based on the difference signal that is an output of the subtractor when a second test signal is input to the signal processing circuit.
    Type: Application
    Filed: June 16, 2020
    Publication date: March 31, 2022
    Inventor: Tadayoshi OKUDA
  • Patent number: 10868533
    Abstract: Electrodes and regions of top plate opposed to electrodes constitute switches that have capacitances varying when the regions of top plate are depressed from top plate toward electrodes. Depression detection circuit calculates the capacitance change amounts of switches indicating changes of the capacitances from a reference value. Depression detection circuit calculates the maximum value and sum of the capacitance change amounts of switches. When the capacitance change amount of at least one switch exceeds threshold and a situation in which the ratio of the maximum value to the sum is equal to or greater than threshold has lasted for the number of repetitions in, depression detection circuit determines that the switch having the maximum value of the capacitance change amount is in a depressed state.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 15, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masami Yamamoto, Yukinobu Tokoro, Shohei Kawagoe, Kojiro Kawasaki, Tadayoshi Okuda, Yosuke Shiota
  • Patent number: 10764682
    Abstract: A control device includes a first communication circuit, a microphone, and a first control circuit.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masami Yamamoto, Tadayoshi Okuda, Yosuke Shiota
  • Publication number: 20200092646
    Abstract: A control device includes a first communication circuit, a microphone, and a first control circuit.
    Type: Application
    Filed: April 20, 2018
    Publication date: March 19, 2020
    Inventors: MASAMI YAMAMOTO, TADAYOSHI OKUDA, YOSUKE SHIOTA
  • Publication number: 20190346959
    Abstract: Electrodes Ex and regions of top plate opposed to electrodes Ex constitute switches SWx that have capacitances varying when the regions of top plate are depressed from top plate toward electrodes Ex. Depression detection circuit calculates the capacitance change amounts of switches SWx indicating changes of the capacitances from a reference value. Depression detection circuit calculates the maximum value and sum of the capacitance change amounts of switches SWx. When the capacitance change amount of at least one switch SWx exceeds threshold TH_EDGE and a situation in which the ratio of the maximum value to the sum is equal to or greater than threshold COMP_LEVELx has lasted for the number of repetitions in SW_DET_COUNT, depression detection circuit determines that the switch having the maximum value of the capacitance change amount is in a depressed state.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: MASAMI YAMAMOTO, YUKINOBU TOKORO, SHOHEI KAWAGOE, KOJIRO KAWASAKI, TADAYOSHI OKUDA, YOSUKE SHIOTA
  • Patent number: 10069468
    Abstract: An audio signal amplification device includes: a clock generation circuit that generates a clock for use in amplifying an audio signal; and a power supply circuit that generates direct current power, which is supplied to the clock generation circuit, from input power. The power supply circuit includes: a constant voltage generation circuit that generates direct current power of a constant voltage from the input power; a first capacitor; a first charging circuit that charges the first capacitor by using the input power; and a selection circuit. The selection circuit selects one direct current power of the direct current power generated in the constant voltage generation circuit and of direct current power charged to the first capacitor, and supplies the selected direct current power to the clock generation circuit.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 4, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Tadayoshi Okuda
  • Publication number: 20170279420
    Abstract: An audio signal amplification device includes: a clock generation circuit that generates a clock for use in amplifying an audio signal; and a power supply circuit that generates direct current power, which is supplied to the clock generation circuit, from input power. The power supply circuit includes: a constant voltage generation circuit that generates direct current power of a constant voltage from the input power; a first capacitor; a first charging circuit that charges the first capacitor by using the input power; and a selection circuit. The selection circuit selects one direct current power of the direct current power generated in the constant voltage generation circuit and of direct current power charged to the first capacitor, and supplies the selected direct current power to the clock generation circuit.
    Type: Application
    Filed: December 24, 2015
    Publication date: September 28, 2017
    Inventor: TADAYOSHI OKUDA
  • Publication number: 20130208086
    Abstract: A 3D video reproduction device configured to reproduce 3D streaming data that includes 3D video data and audio data. The 3D video reproduction device comprises an audio analyzing unit, a parallax setting unit, a video correction unit, and an output unit. The audio analyzing unit is configured to analyze the audio data to determine the scene indicated by the 3D video data. The parallax setting unit is configured to set the amount of parallax that corresponds to the scene based on the audio data analyzed by the audio analyzing unit. The video correction unit is configured to correct the 3D video data based on the amount of parallax set by the parallax setting unit. The output unit is configured to reproduce the corrected 3D video data and output the audio data.
    Type: Application
    Filed: June 1, 2012
    Publication date: August 15, 2013
    Applicant: Panasonic Corporation
    Inventors: Tadayoshi OKUDA, Takuya Sugita
  • Patent number: 8462264
    Abstract: A video scan converter processes a video stream including a first coding unit, which has been obtained by encoding a pair of fields N1 and N2 that has come from a first frame of film video, and a second coding unit, which has been obtained by encoding a pair of a field N3 that has also come from the first frame and a field M1 that has come from a second frame, not the first frame. The video scan converter includes: a decoder, which receives the video stream, decodes the first and second coding units, and sequentially outputs the data of the respective fields N1, N2, N3 and M1; and a scan converter, which generates a frame based on associated two of those fields that have been supplied from the decoder. In outputting a frame associated with the field N3, the scan converter generates the frame based on the fields N1 and N2 without using the data of the field N3.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: June 11, 2013
    Assignee: Panasonic Corporation
    Inventors: Tadayoshi Okuda, Toshiya Noritake
  • Patent number: 8400565
    Abstract: A video scan converter processes a video stream including a first coding unit, which has been obtained by encoding a pair of fields N1 and N2 that has come from a first frame of film video, and a second coding unit, which has been obtained by encoding a pair of a field N3 that has also come from the first frame and a field M1 that has come from a second frame, not the first frame. The video scan converter includes: a decoder, which receives the video stream, decodes the first and second coding units, and sequentially outputs the data of the respective fields N1, N2, N3 and M1; and a scan converter, which generates a frame based on associated two of those fields that have been supplied from the decoder. In outputting a frame associated with the field N3, the scan converter generates the frame based on the fields N1 and N2 without using the data of the field N3.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: March 19, 2013
    Assignee: Panasonic Corporation
    Inventors: Tadayoshi Okuda, Toshiya Noritake
  • Publication number: 20130010064
    Abstract: A video processing device, which can output stereoscopic video information that enables stereoscopic viewing to a video display device, includes an obtaining unit that obtains the stereoscopic video information, a superimposing unit that superimposes additional video information on the stereoscopic video information, and a transmitting unit that transmits parallax information of the additional video information to the video display device, with the parallax information being associated with the stereoscopic video information on which the additional video information is superimposed.
    Type: Application
    Filed: March 24, 2011
    Publication date: January 10, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Tadayoshi Okuda
  • Publication number: 20130002821
    Abstract: A video processing device is a device capable of outputting stereoscopic video information containing a first eye image and a second eye image and enabling stereoscopic viewing to a video display device. The video processing device includes an obtaining unit that obtains the stereoscopic video information which is obtained by coding the first and second eye images in a coding method using different bit rates to the first and second eye images respectively, and a transmitting unit that transmits identification information indicating one of the first and second eye images that is coded with higher bit rate, to the video display device, with the identification information being associated with the decoded stereoscopic video information.
    Type: Application
    Filed: March 24, 2011
    Publication date: January 3, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Tadayoshi Okuda
  • Publication number: 20120162508
    Abstract: A video data conversion apparatus can convert inputted video data in a predetermined scanning format into video data in another scanning format. The inputted video data in the predetermined scanning format is video data at 60 fields per second in a 4:2:2:2 format. The video data in the 4:2:2:2 format is video data in a format where four fields generated from one original image, two fields generated from a next original image, two fields generated from a further next original image, and two fields generated from a further next original image appear periodically in this order. The video data conversion apparatus includes a conversion unit operable to convert the inputted video data into video data at 60 frames per second in a 3:2 pulldown format.
    Type: Application
    Filed: December 28, 2011
    Publication date: June 28, 2012
    Inventor: Tadayoshi OKUDA
  • Publication number: 20110285827
    Abstract: An image display apparatus capable of connecting to an image reproducing apparatus, including: an authentication switchover unit operable to perform mutual authentication with the image reproducing apparatus to switch an own authentication state between a 2D-authenticated state and a 3D-authenticated state; a display switchover unit operable to switch an own display mode between a 3D display mode and a 2D display mode; and an output unit operable to output image display mode information in accordance with the display mode set in the own apparatus in case where the authentication switchover unit sets the own authentication state to the 3D-authenticated state.
    Type: Application
    Filed: May 12, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: SHINICHIROU TAKIGAWA, TADAYOSHI OKUDA, YOSHIKI KUNO, TETSUYA ITANI
  • Publication number: 20110242284
    Abstract: An image reproducing apparatus capable of outputting a 3D image signal or a non-3D image signal which can display a stereoscopic or a non-stereoscopic image to an image display apparatus, including: an AV processing unit operable to input data of contents and generate the 3D or non-3D image signal from the contents data; an output unit operable to output the 3D or non-3D image signal generated by the AV processing unit to the display apparatus in accordance with a 3D image output format being a format for outputting an image signal for stereoscopic display; and a receiving unit operable to receive an instruction inputted by a user.
    Type: Application
    Filed: July 14, 2010
    Publication date: October 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Shinichirou Takigawa, Tadayoshi Okuda, Yoshiki Kuno
  • Publication number: 20100265315
    Abstract: A three-dimensional image combining apparatus includes an obtaining unit configured to obtain data of a main image as an image enabling stereoscopic view, data of an additional image to be combined with the main image and be displayed, and position information for defining a display position in a depth direction of the additional image in stereoscopic view of the additional image, a scaling unit configured to upscale or downscale the main image, an adjusting unit configured to adjust the position information based on a magnification of upscaling or downscaling the main image, and a combining unit configured to combine the additional image with the upscaled or downscaled main image based on the adjusted position information so that the additional image can be viewed stereoscopically.
    Type: Application
    Filed: April 20, 2010
    Publication date: October 21, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: TADAYOSHI OKUDA, SHINICHI KAWAKAMI
  • Publication number: 20090322939
    Abstract: A video scan converter processes a video stream including a first coding unit, which has been obtained by encoding a pair of fields N1 and N2 that has come from a first frame of film video, and a second coding unit, which has been obtained by encoding a pair of a field N3 that has also come from the first frame and a field M1 that has come from a second frame, not the first frame. The video scan converter includes: a decoder, which receives the video stream, decodes the first and second coding units, and sequentially outputs the data of the respective fields N1, N2, N3 and M1; and a scan converter, which generates a frame based on associated two of those fields that have been supplied from the decoder. In outputting a frame associated with the field N3, the scan converter generates the frame based on the fields N1 and N2 without using the data of the field N3.
    Type: Application
    Filed: April 22, 2009
    Publication date: December 31, 2009
    Applicant: Panasonic Corporation
    Inventors: Tadayoshi OKUDA, Toshiya NORITAKE