Abstract: A PLL circuit comprises a phase frequency detector configured to output a phase frequency difference signal with a pulse duration according to a phase difference and a frequency difference between a reference clock signal and a feedback clock signal according to an output clock signal; a charge pump circuit configured to output a charge pump current which is an output current according to the phase frequency difference signal and reduce a charge pump current amount in accordance with a charge pump current amount control signal for reducing the charge pump current amount stepwisely; and a lock detecting unit configured to detect whether or not the feedback clock signal is locked to the reference clock signal and output a lock detection signal when detecting a lock of the reference clock signal and the feedback clock signal