Abstract: A semiconductor device designing method of the present invention corresponds to a method for designing a clock synthesization type semiconductor device, which is comprised of: a rough CTS (clock tree synthesis) step for performing the CTS within an adjustable range in multiple phases; a timing check step for judging whether or not transmission/reception of data are carried out under normal condition based upon a propagation time of data and an arrival time of a clock signal between flip-flops; a detailed timing analyzing step for judging whether or not the transmission/reception of the data can be carried out under the normal condition by switching a phase of a clock signal, or by increasing/decreasing a buffer in a half way of the clock tree as to supply timing of the clock signal; and a re-allocating step of a CLK net, for allocating a phase of such a clock signal which does not cause a timing violation every flip-flop based upon the result of the detailed timing analyzing step.

Abstract: A semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus are provided that implement automatic placement that reflects constraints provided regarding parasitic elements and inter-element variation provided in a real-valued range. A netlist is prepared in advance, a permissible range setting process sets a permissible range relating to elements, a floor plan process creates a floor plan that satisfies the set permissible range using the netlist, an automatic placement process places elements using the created floor plan and extracts routing constraints that realize a permissible range for parasitic elements, and a routing process performs routing in accordance with the extracted routing constraints.

Abstract: A semiconductor integrated circuit manufacturing method and semiconductor integrated circuit manufacturing apparatus are provided that implement automatic placement that reflects constraints provided regarding parasitic elements and inter-element variation provided in a real-valued range. A netlist is prepared in advance, a permissible range setting process sets a permissible range relating to elements, a floor plan process creates a floor plan that satisfies the set permissible range using the netlist, an automatic placement process places elements using the created floor plan and extracts routing constraints that realize a permissible range for parasitic elements, and a routing process performs routing in accordance with the extracted routing constraints.